Problem with Liberate and Verilog-A Model

Hi Cadence Community,

I want to characterize a circuit design using the following software and PDK:

• Virtuoso Studio version IC23.1-64b.ISR7.27 (64-bit addresses)
• LIBERATE Library Characterization Platform (x86_64) Release 23.1.6.074.isr6
• Skywater PDK release 0.0.6 (Version from the Cadence Support website)
• Verilog-A Model from Skywater: https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/tree/main/cells/reram_cell

I did the following steps with Virtuoso:
Create Schematic -> Layout -> LVS -> PEX -> Extract Post Layout Netlist -> Run Post Layout Simulation.

My final design works as expected and contains NMOS transistors as well as the Verilog-A model from Skywater. 

Next, I read the documentation of Liberate and found these discussions in the cadence forum to add the Verilog-A model:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/63102/characterizing-cells-with-verilog-a-models-by-liberate-but-the-model-or-instance-can-not-be-found
https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/42194/characterizing-library-for-emerging-2dfets-with-in-house-va-based-models

I added the instructions mentioned in the threads and documentation to all required files.
After I started the Liberate tool I got the following error message:

In sim.lis:

Error found by spectre during circuit read-in.
ERROR (SFE-874): "/tmp/altos.localhost.localdomain.T20250616102845114901S0100268.7/sim.sp" 2: Cannot run the simulation because syntax error `Unexpected string value "/home/user/Desktop/test_lib/NETLIST/veriloga.va"' was encountered at line 2, column 67. Correct the syntax error and rerun the simulation.

Warning from spectre during circuit read-in.
WARNING (SFE-3266): "/tmp/altos.localhost.localdomain.T20250616102845114901S0100268.7/sim.sp" 2: The first line is treated as a comment following Spice convention. Check the netlist to ensure that the valid content does not start from the first line.

First two lines of sim.sp:

line1: **** Altos spice deck for characterization release 23.1.6.074.isr6
line2: /home/user/Desktop/test_lib/NETLIST/veriloga.va

I tried to switch between different instructions in the control file but with no success.
Below you find the control file.

Does anyone know what could be wrong?

Kind Regards
Felix

# Liberate Example Tcl File

# Set the run directory. Here we use PWD, but in a distributed
# environment, it is recommended to directly specify the full path
# instead of using "PWD"
set rundir $env(PWD)

# Create the directories Liberate will write to.
exec mkdir -p ${rundir}/LDB
exec mkdir -p ${rundir}/LIBRARY
exec mkdir -p ${rundir}/DATASHEET

### Define temperature and default voltage ###
set_operating_condition -voltage 1.8 -temp 25

###Set DSPF to use
#set_var switch_cell_internal_net_name "use_dspf_star_net"
#set_var parse_ignore_duplicate_subckt 1
#set_var extsim_cmd_option "+aps"
set_var extsim_cmd "spectre"
#set_var extsim_deck_header "simulator lang=spice"

### Include Verilog A file
set_var extsim_deck_header $rundir/NETLIST/veriloga.va
#set_var extsim_model_include $rundir/NETLIST/veriloga.va
define_leafcell -extsim_model -type black_box -pin_position {0 1} {sky130_fd_pr_reram__reram_cell}
#define_leafcell -element -extsim_model -type black_box -pin_position {0 1} {sky130_fd_pr_reram__reram_cell}

## Load template information for each cell ##
source ${rundir}/TEMPLATE/template_example.tcl

## Load Spice models and subckts ##
set spicefiles $rundir/NETLIST/sky130.lib.scs

foreach cell $cells {
lappend spicefiles ${rundir}/NETLIST/${cell}.sp
}

read_spice -format spectre $spicefiles

## Characterize the library for NLDM (default), CCS and ECSM timing.
# char_library -extsim spectre -ccs -ecsm -cells ${cells}
char_library -extsim spectre -cells ${cells}

## Save characterization database for post-processing ##
write_ldb ${rundir}/LDB/my_lib.ldb

## Generate a .lib with ccs, ecsm ###
# write_library -overwrite -ccs ${rundir}/LIBRARY/my_lib_ccs.lib
# write_library -overwrite -ecsm ${rundir}/LIBRARY/my_lib_ecsm.lib
write_library -overwrite ${rundir}/LIBRARY/my_lib.lib

## Generate all .v files
write_verilog ${rundir}/VERILOG/my_lib_ND.v
write_verilog -specparams -table_style min-avg-max ${rundir}/VERILOG/my_lib_D

## Generate html datatsheet ###
write_datasheet -format html -dir ${rundir}/DATASHEET/ tt