Virtuoso AMS NOUNIT error with Xcelium - Not caching libraries

I am trying to run very basic circuits via the Virtuoso AMS simulator by invocation of the Xcelium toolchain through an ADE Explorer maestro view.  My topcell consists of a basic Verilog clock generator module feeding into a CMOS level shifter:

I have created a configuration for this via HED using the AMS template, and use this configuration as the "design" in the ADE Explorer test.  Connect rules are set to a default "full fast" setting using 1V nominal, which is well within the capabilities of the CMOS.

When I Netlist and Run, the simulator window pops up with the following output:

xrun(64): 24.09-s013: (c) Copyright 1995-2025 Cadence Design Systems, Inc.
TOOL: xrun(64) 24.09-s013: Started on Oct 28, 2025 at 21:54:51 EDT
xrun

-f xrunArgs
-UNBUFFERED
-cdslib ./cds.lib
-errormax 50
-status
-nowarn DLNOHV
-nowarn DLCLAP
-v93
-incdir <sanitized>
-ade
-timescale 1ns/1ns
-vtimescale 1ns/1ns
-delay_mode None
-novitalaccl
-access r
-noparamerr
-amspartinfo ../psf/partition.info
-rnm_partinfo
-modelincdir <sanitized>/Cadence_22nm/
./spiceModels.scs
./amsControlSpectre.scs
-input ./probe.tcl
-run
-exit
-xmsimargs "+amsrawdir ../psf"
-spectre_args "-ahdllibdir <sanitized>/Cadence_Sim/spi_master_trx_verilog/clk_gen_tb/maestro/results/maestro/ExplorerRun.0/sharedData/CDS/ahdl/input.ahdlSimDB"
-spectre_args +logstatus
-simcompatible_ams spectre
-name spi_master_trx_verilog.clk_gen_tb:auto_config
-allowredefinition
-amsbind
-top spi_master_trx_verilog.clk_gen_tb:schematic
-top cds_globals
./netlist.vams
./ie_card.scs
-f ./textInputs
-amscompilefile "file:<Sanitized>AMS_Verilog_tests/clk_gen/verilogams/verilog.vams lib:AMS_Verilog_tests cell:clk_gen view:verilogams"
-makelib spi_master_trx_verilog
-makelib axstepko_spi
-endlib
./cds_globals.vams
-l ../psf/xrun.log
-spectre_args +aps

file: ./netlist.vams
file: ./cds_globals.vams
module worklib.cds_globals:vams
errors: 0, warnings: 0
file: <sanitized>Cadence_22nm/AMS_Verilog_tests/clk_gen/verilogams/verilog.vams
module AMS_Verilog_tests.clk_gen:verilogams
errors: 0, warnings: 0
xmvlog: *W,SPDUSD: Include directory <sanitized>Cadence_22nm/ given but not used.
Total errors/warnings found outside modules and primitives:
errors: 0, warnings: 1
xmvlog: Memory Usage - Current physical: 25.6M, Current virtual: 61.3M, Peak physical: 25.6M
xmvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 54.5% cpu)
AMSD Universal Connect Module UCM is enabled.
Caching library 'AMS_Verilog_tests' ....... Done
Caching library 'worklib' ....... Done
xmelab: *E,NOUNIT: Unable to find a unit named 'spi_master_trx_verilog.clk_gen_tb:schematic' in the libraries.
xmelab: Memory Usage - Final: 53.8M, Peak: 53.8M, Peak virtual: 142.2M
xmelab: CPU Usage - 0.0s system + 0.0s user = 0.1s total (0.2s, 32.3% cpu)
xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 1), exiting.
TOOL: xrun(64) 24.09-s013: Exiting on Oct 28, 2025 at 21:55:04 EDT (total: 00:00:13)

It appears that during some part of elaboration (xmelab?), the process fails to cache the library "spi_master_trx_verilog" and the "axstepko_spi" library, which contains the cell I wish to simulate and in general needs to be used in design.  I have had success running AMS simulations from other Cadence tutorials and saw the simulator caching all of the required libraries, and so I suspect that something to do with library paths is the problem here.  The "spi_master_trx_verilog" is attached to the master library via an INCLUDE statement in the root cds.lib: