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Virtuoso AMS NOUNIT error with Xcelium - Not caching libraries

AS202502163432

I am trying to run very basic circuits via the Virtuoso AMS simulator by invocation of the Xcelium toolchain through an ADE Explorer maestro view.  My topcell consists of a basic Verilog clock generator module feeding into a CMOS level shifter:

I have created a configuration for this via HED using the AMS template, and use this configuration as the "design" in the ADE Explorer test.  Connect rules are set to a default "full fast" setting using 1V nominal, which is well within the capabilities of the CMOS.

 

When I Netlist and Run, the simulator window pops up with the following output:

xrun(64): 24.09-s013: (c) Copyright 1995-2025 Cadence Design Systems, Inc.
TOOL: xrun(64) 24.09-s013: Started on Oct 28, 2025 at 21:54:51 EDT
xrun


-f xrunArgs
-UNBUFFERED
-cdslib ./cds.lib
-errormax 50
-status
-nowarn DLNOHV
-nowarn DLCLAP
-v93
-incdir <sanitized>
-ade
-timescale 1ns/1ns
-vtimescale 1ns/1ns
-delay_mode None
-novitalaccl
-access r
-noparamerr
-amspartinfo ../psf/partition.info
-rnm_partinfo
-modelincdir <sanitized>/Cadence_22nm/
./spiceModels.scs
./amsControlSpectre.scs
-input ./probe.tcl
-run
-exit
-xmsimargs "+amsrawdir ../psf"
-spectre_args "-ahdllibdir <sanitized>/Cadence_Sim/spi_master_trx_verilog/clk_gen_tb/maestro/results/maestro/ExplorerRun.0/sharedData/CDS/ahdl/input.ahdlSimDB"
-spectre_args +logstatus
-simcompatible_ams spectre
-name spi_master_trx_verilog.clk_gen_tb:auto_config
-allowredefinition
-amsbind
-top spi_master_trx_verilog.clk_gen_tb:schematic
-top cds_globals
./netlist.vams
./ie_card.scs
-f ./textInputs
-amscompilefile "file:<Sanitized>AMS_Verilog_tests/clk_gen/verilogams/verilog.vams lib:AMS_Verilog_tests cell:clk_gen view:verilogams"
-makelib spi_master_trx_verilog
-makelib axstepko_spi
-endlib
./cds_globals.vams
-l ../psf/xrun.log
-spectre_args +aps


file: ./netlist.vams
file: ./cds_globals.vams
module worklib.cds_globals:vams
errors: 0, warnings: 0
file: <sanitized>Cadence_22nm/AMS_Verilog_tests/clk_gen/verilogams/verilog.vams
module AMS_Verilog_tests.clk_gen:verilogams
errors: 0, warnings: 0
xmvlog: *W,SPDUSD: Include directory <sanitized>Cadence_22nm/ given but not used.
Total errors/warnings found outside modules and primitives:
errors: 0, warnings: 1
xmvlog: Memory Usage - Current physical: 25.6M, Current virtual: 61.3M, Peak physical: 25.6M
xmvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 54.5% cpu)
AMSD Universal Connect Module UCM is enabled.
Caching library 'AMS_Verilog_tests' ....... Done
Caching library 'worklib' ....... Done
xmelab: *E,NOUNIT: Unable to find a unit named 'spi_master_trx_verilog.clk_gen_tb:schematic' in the libraries.
xmelab: Memory Usage - Final: 53.8M, Peak: 53.8M, Peak virtual: 142.2M
xmelab: CPU Usage - 0.0s system + 0.0s user = 0.1s total (0.2s, 32.3% cpu)
xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 1), exiting.
TOOL: xrun(64) 24.09-s013: Exiting on Oct 28, 2025 at 21:55:04 EDT (total: 00:00:13)

It appears that during some part of elaboration (xmelab?), the process fails to cache the library "spi_master_trx_verilog" and the "axstepko_spi" library, which contains the cell I wish to simulate and in general needs to be used in design.  I have had success running AMS simulations from other Cadence tutorials and saw the simulator caching all of the required libraries, and so I suspect that something to do with library paths is the problem here.  The "spi_master_trx_verilog" is attached to the master library via an INCLUDE statement in the root cds.lib:

INCLUDE <sanitized>/Cadence_22nm/SPI-Master-TRX-Verilog/cds.lib
Inside of the referenced cds.lib:
DEFINE spi_master_trx_verilog <sanitized>Cadence_22nm/SPI-Master-TRX-Verilog/spi_master_trx_verilog
 
Any suggestions on what I should try and check are greatly appreciated, this has been very confusing to debug thus far!

Parents
  • AS202502163432

    Still looking for help on this.  Is there a way to list out the available libraries that Xcelium can cache during elaboration?

Reply
  • AS202502163432

    Still looking for help on this.  Is there a way to list out the available libraries that Xcelium can cache during elaboration?

Children
  • Andrew Beckett
    in reply to AS202502163432

    Your best bet would be to contact customer support - log into http://ask.cadence.com and then use the Case menu to submit a case.

    It looks as if the blocks in question may not have been netlisted and hence not compiled (I think this "Caching" is a red herring). Your log (which you've sanitised) doesn't appear to show any modules having been compiled from the netlist.vams so maybe the schematics from this spi_master library weren't netlisted. It's really hard to tell without more info about how these are instantiated, what's in the netlist, any messages produced and so on. A support case would make this much easier than trying to communicate via a public forum (which is not a substitute for regular customer support).

    Andrew

  • AS202502163432
    in reply to AS202502163432

    When I examine the netlist.vams file it is empty aside from including disciplines and userDisciplines. This is not the case when netlisting inside of the Virtuoso ADE Explorer interface itself.

    How can I, in general, compile/netlist a library/cell?

    P.S.  The <sanitized> field all points to the same directory which was hidden for privacy.

  • AS202502163432
    in reply to AS202502163432

    This is what is inside of the empty netlist.vams:

    // AMS netlist generated by the AMS Unified netlister
    // IC subversion:  IC23.1-64b.ISR11.29 
    // Xcelium version: 24.09-s013
    // Copyright(C) 2005-2009, Cadence Design Systems, Inc
    // User: as5352 Pid: 2723230
    // Design library name: spi_master_trx_verilog
    // Design cell name: clk_gen_tb
    // Design view name: auto_config
    // Solver: Spectre

    `include "disciplines.vams"
    `include "userDisciplines.vams"
    // HDL file - spi_master_trx_verilog, clk_gen_spi_test, verilogams.

    The clk_gen_spi_test was copied from another library where I am in-fact able to successfully simulate out of, and whose netlist.vams is populated with much more "useful" information about module connectivity, etc..  For whatever reason, this spi_master_trx_verilog library has this problem of generating an empty netlist.  

    The library spi_master_trx_verilog does reside within a Git repository, but I have been able to run Spectre out of this library with no problem.

  • Andrew Beckett
    in reply to AS202502163432
    AS202502163432 said:

    When I examine the netlist.vams file it is empty aside from including disciplines and userDisciplines. This is not the case when netlisting inside of the Virtuoso ADE Explorer interface itself.

    But the netlist.vams is being generated by ADE so I don't understand how it can be both empty and not empty at the same time.

    Did you contact customer support as I suggested?

    Andrew

  • AS202502163432
    in reply to AS202502163432

    It would appear that the netlist generated by ADE Explorer (through the manual Simulation -> Netlist -> Create option)  is not the same file as the one generated through a "Netlist and Run" which invokes the xrun command similar to the one in my original post.  The one available when clicking on the "netlist.vams" in the xrun log is empty.

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