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  3. PSS + PSTB for Buck converter

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PSS + PSTB for Buck converter

TH202510293247
TH202510293247 21 days ago

Hi,

I am new to power converters. I am currently working on a controller design for buck. I wanted to simulate the stability response for the circuit. While pss is working as per expectation, pstb is giving '0' (-6.4kdB) loop gain and phase. I am using voltage source as probe at the o/p to break the circuit. Can anyone help me - what i am missing here? 

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  • Frank Wiedmann
    Frank Wiedmann 20 days ago

    If you don't show us your schematic, this will be very difficult. You have to put the probe at a node of the loop that is not being switched, because pstb examines sideband 0.

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  • TH202510293247
    TH202510293247 20 days ago in reply to Frank Wiedmann

    Sorry about not providing the details....

    Please see below:

    PSS and PSTB settings:

    PSS results:

    PSTB results:

    When I res-simulated the loop gain magnitude is not exactly zero but very low!!

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  • nrk1
    nrk1 19 days ago in reply to TH202510293247

    What is inside the block on the top left? Also, you have gnd! and VSS. I guess they are connected elsewhere. (I use iprobe or diffstbprobe as probes for stb/pstb-though the voltage source also works-another thing to try).

    Nagendra

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  • TH202510293247
    TH202510293247 19 days ago in reply to nrk1

    The top left is a model of power stage (switches from analog lib).
    Yes VSS and gnd! are shorted with a vdc in the testbench.

    Tried using iprobe, however, the pstb results didn't change.

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  • nrk1
    nrk1 19 days ago in reply to TH202510293247

    Strange. I  guess you could try other locations (between the CCVS and the loop filter or the loop filter and the VCVS) for the probe and see if the results change. 

    Nagendra

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  • Frank Wiedmann
    Frank Wiedmann 19 days ago in reply to TH202510293247

    What happens if you select gnd! as the Local Ground Name (or just leave this field empty)?

    If there are ideal components or Verilog-A models in your circuit, you should also watch out for the problem described at https://designers-guide.org/forum/YaBB.pl?num=1189658426 

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  • SA202512302438
    SA202512302438 19 days ago

    What happens if you do pss+pac for the converter + PWM generator (E0 in your circuit) by adding a vdc source at the PWM ramp generator and make its PAC magnitude as 1. Do you see any gain from the pac source to the output? As per theory this should give you the frequency response of the converter and PWM circuit.

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  • TH202510293247
    TH202510293247 15 days ago in reply to nrk1

    I tried placing the pstb probes at different places - the results are still absurd. I suppose I am missing something but unable to crack it unfortunately.

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  • TH202510293247
    TH202510293247 15 days ago in reply to Frank Wiedmann

    Hi Frank, tried having only one ground (gnd!) in the schematic - that didn't help either 

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  • TH202510293247
    TH202510293247 15 days ago in reply to SA202512302438

    As part of debugging I actually did a simple tb with only the ramp and i/p passed through a comparator to generate a PWM waveform. To my surprise, I found that the pac gain from i/p to PWM o/p is giving '0'.

    I guess the problem lies here itself....!!

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