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Recovering "actionable" netlist from GDS II

GS202507021424

I'm interested in the extent to which one can recover usable netlist information from a GDS IIfile.

Assuming the GDS II was produced based on [gpdk|gsclib|giolib]045, and the original schematic (or Verilog source) was subsequently lost, I'm wondering if it is possible to recover enough information about the standard cell netlist to attempt redoing the synthesis (Genus) and place-and-route (Innovus) flows (presumably after having made some additional changes/edits to the netlist).

Right now, I can stream-import the GDS II into Virtuoso as a layout view. I can run Assura LVS to compare this against a dummy schematic: even though the comparison itself will fail, the run will produce an extracted netlist from the layout as a byproduct (*.ldb and/or *.lnnfiles, apparently generated via dfIIToVdb).

I dug around the documentation I could find, and while there's a lot of talk about dfIIToVldb, there's nothing on dfIIToVdb, and I'm a bit confused about what the difference might be between the two, and the output they produce.

I'm wondering what tools there exist to then view and/or convert the extracted netlist information (e.g., the aforementioned *.ldb/*.lnn file formats), into either Verilog or anything else that can be edited and passed back as input to Genus & Innovus for subsequent synthesis, placement, and routing.

Also, I wonder if there's a less roundabout way of extracting actionable netlist information (down to standard cells) directly from a GDS II file...

Any advice much appreciated!

Parents
  • Andrew Beckett

    I didn't see this post, but you could use vldbToSpice (or vldbToCdl) on the *.lnn file. There's nothing to output to Verilog. I suspect it might be a challenge to use the result as it will be missing meaningful names, but maybe it's better than nothing.

    Andrew

  • GS202507021424
    in reply to Andrew Beckett

    The other problem I'm running into is importing the *.cdl file produced from the *.lnnbyproduct of LVS.

    When I try Virtuoso → File → Import → Spice..., and fill out the Input pane:

    • Netlist File: .../chip_lnn.cdl
    • Netlist Language: CDL
    • Reference Library List: gpdk045 gsclib045 giolib045

    ... and the Output pane:

    • Log File: spiceIn.log
    • Output Library: foo
    • Process Technoloy File: Output View Type: netlist

    ... I end up with the following error:

    ...
No subckt parameters for this module
    Instance: MavD13_1
    Instance has master: 'mos' model/subtype: 'g45p2svt'

        Master Cell: 'mos'.
        Did not find 'gpdk045.mos:symbol'.
        Did not find 'gsclib045.mos:symbol'.
        Did not find 'giolib045.mos:symbol'.
ERROR (SPICEIN-24): Spice In did not find the symbol view of the master cell 'mos' of the instance
...

    There are references to the following devices throughout the *.cdl:

    g45n1svt
g45n2svt
g45p1svt
g45p2svt

    ... and I wonder why these aren't matched to gpdk045, which is (AFAIK) correctly configured in my cds.lib...

    Any further help much appreciated!

Reply
  • GS202507021424
    in reply to Andrew Beckett

    The other problem I'm running into is importing the *.cdl file produced from the *.lnnbyproduct of LVS.

    When I try Virtuoso → File → Import → Spice..., and fill out the Input pane:

    • Netlist File: .../chip_lnn.cdl
    • Netlist Language: CDL
    • Reference Library List: gpdk045 gsclib045 giolib045

    ... and the Output pane:

    • Log File: spiceIn.log
    • Output Library: foo
    • Process Technoloy File: Output View Type: netlist

    ... I end up with the following error:

    ...
No subckt parameters for this module
    Instance: MavD13_1
    Instance has master: 'mos' model/subtype: 'g45p2svt'

        Master Cell: 'mos'.
        Did not find 'gpdk045.mos:symbol'.
        Did not find 'gsclib045.mos:symbol'.
        Did not find 'giolib045.mos:symbol'.
ERROR (SPICEIN-24): Spice In did not find the symbol view of the master cell 'mos' of the instance
...

    There are references to the following devices throughout the *.cdl:

    g45n1svt
g45n2svt
g45p1svt
g45p2svt

    ... and I wonder why these aren't matched to gpdk045, which is (AFAIK) correctly configured in my cds.lib...

    Any further help much appreciated!

Children
  • Andrew Beckett
    in reply to GS202507021424
    GS202507021424 said:
    and I wonder why these aren't matched to gpdk045, which is (AFAIK) correctly configured in my cds.lib

    You would need to provide some device mapping file with SPICE IN to map the model names back to the actual devices in the library. The model names don't match the component names.

    Andrew

  • GS202507021424
    in reply to Andrew Beckett

    Thanks for the hint! Since this turned out to be a non-trivial endeavor, here's the map file I loaded (via the Device Map pane/tab of the Spice In dialog), as a syntax example for anyone else who might run into a similar problem and find this thread:

    devSelect := mos nmos1v
        propMatch := subtype g45n1svt
devSelect := mos nmos2v
        propMatch := subtype g45n2svt
devSelect := mos pmos1v
        propMatch := subtype g45p1svt
devSelect := mos pmos2v
        propMatch := subtype g45p2svt

    This, along with a bit of manual massaging of the *.cdl file, allowed me to import into virtuoso as either netlist or schematic.

    Thanks again!

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