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PVS LVS with added external netlist

GBlasco

Hi everyone,

I'm trying to run LVS check using PVS. I'd like to include an external netlist and don't seem to do it correctly. 

The PVS version is : 

Cadence PVS version 22.2 ISR2

The schematic is a simple transmission gate, including 2 inverter cells.

I have the netlist of the inverter and would like to attach it for the LVS check.

Here is a schreenshot of the schematic:

In the PVS LVS Run Submission Form, in "Input" section, I select DFII option for the schematic. 

To attach the inverter netlist, I selecte "Use Existing Include File". Here is a screenshot:

The include file looks as follows (real path ommitted here):

.include_spice "…file_path/inverter.spi"

Results show that the inverters are note recognized.

Any support on this would be highly appreciated.

Thanks!

  • pchris

    Hi,

    Your inverter cells, do they have a schematic?

    The 'view list' I see in your screen shot is 'auCdl schematic'. From your description you want netlisting not to descend into your schematic so one option could be to copy the inverter symbol view to a view named 'auCdl'. Netlisting would then not descend into the schematic view and the definition for the inverter would be the one from the include file you are specifying.

    If this is not the issue or your inverter cell is in a read only library this may not be an option. Should this be the case please include details of the LVS error you are seeing.

    Thanks,

    Chris

  • GBlasco
    in reply to pchris

    Hi Chris, 

    Thanks for your reply. My inverter cells do have a schematic view, but it consists only of the ports. The internal circuit is described in an external netlist provided by the foundry.

    This netlist is actually a read only library, do you see a problem here? 

    Somehow I am not able to attach figures in this post, however, this is the LVS error message:

    Layout Inst : ** missing inst ** | Schematic Inst : XI2
    Layout Model: | Schematic Model: INV2
    ========================================+==================================(mi 1)


    Layout Inst : ** missing inst ** | Schematic Inst : XI3
    Layout Model: | Schematic Model: INV2
    ========================================+==================================(mi 2)


    Layout Insts: X12/M2 @(1.700,9.705) | Schematic Insts: ** missing inst **
    : X12/M0 @(1.700,8.235) | : ** missing inst **
    Layout Model: INV## | Schematic Model:
    ========================================+==================================(mi 3)


    Layout Insts: X13/M2 @(4.065,9.705) | Schematic Insts: ** missing inst **
    : X13/M0 @(4.065,8.235) | : ** missing inst **
    Layout Model: INV## | Schematic Model:

    As you can see, it does recognize the digital cells in the schematic, but it finds the corresponding transistors in the layout.

    Any suggestion? Thanks for your support.

    Guillermo

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