PVS LVS with added external netlist

Hi,

Your inverter cells, do they have a schematic?

The 'view list' I see in your screen shot is 'auCdl schematic'. From your description you want netlisting not to descend into your schematic so one option could be to copy the inverter symbol view to a view named 'auCdl'. Netlisting would then not descend into the schematic view and the definition for the inverter would be the one from the include file you are specifying.

If this is not the issue or your inverter cell is in a read only library this may not be an option. Should this be the case please include details of the LVS error you are seeing.

Thanks,

Chris

Hi Chris, 

Thanks for your reply. My inverter cells do have a schematic view, but it consists only of the ports. The internal circuit is described in an external netlist provided by the foundry.

This netlist is actually a read only library, do you see a problem here? 

Somehow I am not able to attach figures in this post, however, this is the LVS error message:

Layout Inst : ** missing inst ** | Schematic Inst : XI2
Layout Model: | Schematic Model: INV2
========================================+==================================(mi 1)


Layout Inst : ** missing inst ** | Schematic Inst : XI3
Layout Model: | Schematic Model: INV2
========================================+==================================(mi 2)


Layout Insts: X12/M2 @(1.700,9.705) | Schematic Insts: ** missing inst **
: X12/M0 @(1.700,8.235) | : ** missing inst **
Layout Model: INV## | Schematic Model:
========================================+==================================(mi 3)


Layout Insts: X13/M2 @(4.065,9.705) | Schematic Insts: ** missing inst **
: X13/M0 @(4.065,8.235) | : ** missing inst **
Layout Model: INV## | Schematic Model:

As you can see, it does recognize the digital cells in the schematic, but it finds the corresponding transistors in the layout.

Any suggestion? Thanks for your support.

Guillermo

Hi Guillermo,

Thank you for the additional details.

On the PVS LVS run submission GUI, Input section there is a cyclic field for controlling how the netlist is created or if an existing netlist is used. By default it is set to ‘Create CDL’, there is also the option ‘auCDL’. This invokes the ‘PVS Internal Netlister’ which has slightly different behaviour. This is detailed in the PVS User Guide in the section Running LVS -> ‘Difference Between Standard CDL Netlister and PVS Internal Netlister’. Of note is this section:

❑ With auCDL/auLVS modes, when the PVS netlister sees a symbol but does not find

a schematic or a stopping cellview, it adds the following information to the netlist and

continues to process the rest of the schematic hierarchy.

.subckt <Name> <pins>

*PVSCELL netlisted from <name> symbol

*.generic no

.ends <Name>

You can then include a CDL file that contains the description for all the leaf cells that

did not have stopping views. PVS comparison will read the CDL description from

the include file.

I tried this with a schematic like the one you included above and using a modified version on an INV cell from one or our generic std cell libs. All worked fine, please try and let us know how you get on.

Best regards,

     Chris

Hi Guillermo,

Thank you for the additional details.

On the PVS LVS run submission GUI, Input section there is a cyclic field for controlling how the netlist is created or if an existing netlist is used. By default it is set to ‘Create CDL’, there is also the option ‘auCDL’. This invokes the ‘PVS Internal Netlister’ which has slightly different behaviour. This is detailed in the PVS User Guide in the section Running LVS -> ‘Difference Between Standard CDL Netlister and PVS Internal Netlister’. Of note is this section:

❑ With auCDL/auLVS modes, when the PVS netlister sees a symbol but does not find

a schematic or a stopping cellview, it adds the following information to the netlist and

continues to process the rest of the schematic hierarchy.

.subckt <Name> <pins>

*PVSCELL netlisted from <name> symbol

*.generic no

.ends <Name>

You can then include a CDL file that contains the description for all the leaf cells that

did not have stopping views. PVS comparison will read the CDL description from

the include file.

I tried this with a schematic like the one you included above and using a modified version on an INV cell from one or our generic std cell libs. All worked fine, please try and let us know how you get on.

Best regards,

     Chris