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Issue with Missing Layout in TSMC 65nm PDK

DY202601279011

Hi everyone,

I'm currently workingon a chip design using the TSMC 65nm PDK. However,I encountered an issue where MOSFET layout instances (e.g., nch/pch) appear only as boxes with an “X” instead of generating the actual layout.The following warnings are reported in the CIW: *WARNING* (DB-220706): The Pcell plug-in for super master 'tsmcN65/pch/layout' could not be loaded: Cannot find IPcell 'cnDloPcell': Pcell evaluator 'cnDloPcell' not found: Plug-in Registration File Not Found: Plug-in file /opt/eda/cadence/IC618/share/oa/data/plugins/cnDloPcell.plg... *WARNING* (DB-220704): The Pcell super master 'tsmcN65/pch/layout' is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is not a supported feature.

Interestingly, other devices in the same PDK, such as BJTs, can generate layout correctly. In addition, if I directly open the MOSFET layout view inside the PDK library, the layout can be displayed without errors. The issue only occurs when instantiating MOS devices in a user design.

I'd greatly appreciate any suggestions on how to resolve this issue. Thank you very much for your time!

Parents
  • Andrew Beckett

    It sounds as if you're using the version of the PDK using non-SKILL PCells (PyCells) and that the plugin has not been configured or is not running correctly. This is a flow we (as Cadence) do not support, and the recommendation would be to use the version of the PDK which uses SKILL PCells. I can't answer with details because it almost certainly depends on the specific 65nm technology you're using, but getting the SKILL PCell-based PDK is the right way to do this.

    Regards,

    Andrew

Reply
  • Andrew Beckett

    It sounds as if you're using the version of the PDK using non-SKILL PCells (PyCells) and that the plugin has not been configured or is not running correctly. This is a flow we (as Cadence) do not support, and the recommendation would be to use the version of the PDK which uses SKILL PCells. I can't answer with details because it almost certainly depends on the specific 65nm technology you're using, but getting the SKILL PCell-based PDK is the right way to do this.

    Regards,

    Andrew

Children
  • DY202601279011
    in reply to Andrew Beckett

    Hi Andrew,

    Thank you very much for the clarification. That makes sense.

    In my case, I am working in an academic environment and unfortunately do not have direct access to alternative versions of the TSMC 65nm PDK (e.g., a SKILL PCell–based release). I was wondering whether there are any known Virtuoso versions or patch levels that are known to work more reliably with the non-SKILL (PyCell-based) 65nm PDKs, as this PDK is actively used by a collaborating research group in our institute.

    In other words, would reinstalling or switching to a different supported Virtuoso release (for example, an older IC6.1.x build) be a reasonable workaround in such cases, or is the SKILL PCell–based PDK strictly required regardless of the tool version?

    Any guidance you can share would be greatly appreciated.

    Best regards.

  • Andrew Beckett
    in reply to DY202601279011

    As I said, Cadence does not support non-SKILL PCells, so we can't really provide any advice on how to use them. However, it may just be that the PDK has not been configured correctly and so the plugin can't be found because of that. There should be instructions with the PDK telling you how to do this. Or it might be that the plugin shared library is incompatible with the operating system or IC version you're using - you should check the PDK instructions for that.

    I'd be surprised that even in an academic environment that you can't access a current version of the PDK which is suitable for the tools you are using.

    Andrew

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