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How to make stack for transistor

RM202605273230

Dear Sir/Ma’am,

I am currently trying to implement transistor stacking in Cadence Virtuoso in such a way that when I increase a parameter (for example, ns), the transistor internally creates stacked devices while still displaying a single transistor symbol in the schematic.

Initially, I attempted to achieve this by:

Adding an ns parameter in the CDF,

Writing a callback function using SKILL code.

However, I observed that increasing the parameter was not actually generating additional stacked transistors internally. Later, I came to understand that this functionality may require the use of a PCell implementation rather than only CDF callbacks.

I also explored modgen, but I learned that it mainly assists in generating proper stacked structures in layout and does not automatically create stacked devices in the schematic through parameter changes.

Could you please guide me on the correct procedure for implementing transistor stacking in the schematic using PCells? 

Any guidance or resources would be greatly appreciated.

Thank you for your time and support.

Parents
  • RM202605273230

    Dear Sir/Ma’am,

    I am currently trying to implement transistor stacking in Cadence Virtuoso in such a way that when I increase a parameter (for example, ns), the transistor internally creates stacked devices while still displaying a single transistor symbol in the schematic.

    Initially, I attempted to achieve this by:

    • Adding an ns parameter in the CDF,
    • Writing a callback function using SKILL code.

    However, I observed that increasing the parameter was not actually generating additional stacked transistors internally. Later, I came to understand that this functionality may require the use of a PCell implementation rather than only CDF callbacks.

    I also explored modgen, but I learned that it mainly assists in generating proper stacked structures in layout and does not automatically create stacked devices in the schematic through parameter changes.

    Could you please guide me on the correct procedure for implementing transistor stacking in the schematic using PCells? 

    Any guidance or resources would be greatly appreciated.

    Thank you for your time and support.

Reply
  • RM202605273230

    Dear Sir/Ma’am,

    I am currently trying to implement transistor stacking in Cadence Virtuoso in such a way that when I increase a parameter (for example, ns), the transistor internally creates stacked devices while still displaying a single transistor symbol in the schematic.

    Initially, I attempted to achieve this by:

    • Adding an ns parameter in the CDF,
    • Writing a callback function using SKILL code.

    However, I observed that increasing the parameter was not actually generating additional stacked transistors internally. Later, I came to understand that this functionality may require the use of a PCell implementation rather than only CDF callbacks.

    I also explored modgen, but I learned that it mainly assists in generating proper stacked structures in layout and does not automatically create stacked devices in the schematic through parameter changes.

    Could you please guide me on the correct procedure for implementing transistor stacking in the schematic using PCells? 

    Any guidance or resources would be greatly appreciated.

    Thank you for your time and support.

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