Custom IC Design

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Discussion

Clarification on Simulation Failures with Max. Jobs > 1 in ADE Assembler

Category: Custom IC Design

By baltaci

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started 11 months ago

0 replies • 886 views
Discussion

How to run Assura Open Run from the command line?

Category: Custom IC Design

By LoVyacheslavvVEMs

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started 11 months ago

0 replies • 2406 views
Discussion

Clicking Check and Save in Verilog Editor of Virtuoso returns error 'Extract Failed for Cellview"

Category: Custom IC Design

By DK202409295316

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started 11 months ago

0 replies • 1487 views
Discussion

Celsius CFD Crashing after clicking simulation button

Category: Custom IC Design

By HSDROP

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started 11 months ago

0 replies • 2355 views
Discussion

How to Set Up a Config View to Easily Switch Between Schematic and Calibre of DUT for Multiple Testbenches?

Category: Custom IC Design

By Meraj Ahmad

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updated 11 months ago by Meraj Ahmad

2 replies • 4463 views
Discussion

AMS simvision cannot load big psf.trn

Category: Custom IC Design

By gkasap92

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started 11 months ago

0 replies • 2509 views
Discussion

Force virtuoso (Layout XL) to NOT create warning markers in design

Category: Custom IC Design

By CSCNalu

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updated 11 months ago by RobMan

2 replies • 3894 views
Discussion

Characterization of Full adder that use transmission gates using liberate

Category: Custom IC Design

By TM20240913386

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updated over 1 year ago by TM20240913386

1 replies • 3076 views
Discussion

error when generating snp files from a variable

Category: Custom IC Design

By TommasoF

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updated over 1 year ago by TommasoF

3 replies • 3251 views
Discussion

ddt VerilogA usage

Category: Custom IC Design

By AndreaD

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started over 1 year ago

0 replies • 2773 views
Discussion

Display Resource Editor: Different Colors for Schematic and Layout Axis

Category: Custom IC Design

By sgcad

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updated over 1 year ago by sgcad

3 replies • 3991 views
Discussion

Quantus not running an returning error with no description

Category: Custom IC Design

By Awab

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updated over 1 year ago by ConradJ

1 replies • 4072 views
Discussion

How to get maximum value of s11 Trace

Category: Custom IC Design

By NS202408066722

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updated over 1 year ago by NS202408066722

2 replies • 3013 views
Discussion

Author and library name in sheet border

Category: Custom IC Design

By DomiHammerfall

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updated over 1 year ago by DomiHammerfall

2 replies • 3425 views
Discussion

Error using probe terminal for dspf stb analysis

Category: Custom IC Design

By unSkilled

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updated over 1 year ago by Andrew Beckett

1 replies • 3612 views

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