Custom IC Design

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Discussion

Filter in ADE output results table for "eval error" and further filtering

Category: Custom IC Design

By StephanWeber

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started over 3 years ago

0 replies • 930 views
Discussion

VerilogA $abstime limitation to 2pi

Category: Custom IC Design

By Ajmal Hussian

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updated over 3 years ago by Andrew Beckett

6 replies • 10160 views
Discussion

While implementing SENT Rx Tx interface, the operating voltage is 5V in most of the paper for 0.18u technology, I am using 0.03u technology, kindly suggest the suitable voltage for this? cause if I am using high voltage MOS still not working?

Category: Custom IC Design

By CadenSr

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updated over 3 years ago by FormerMember

1 replies • 787 views
Discussion

How to add variable in Model file and Control the variable from ADE

Category: Custom IC Design

By AmarDas

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updated over 3 years ago by AmarDas

2 replies • 7953 views
Discussion

Does anyone know SUB layer used by Global Foundries 7sw

Category: Custom IC Design

By bford33

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started over 3 years ago

0 replies • 7349 views
Discussion

How to disable or automatically approve ADE assembler message 5067

Category: Custom IC Design

By alexstepanov75

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updated over 3 years ago by Andrew Beckett

1 replies • 7747 views
Discussion

Convergence Problem in Symica

Category: Custom IC Design

By SOU1995

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updated over 3 years ago by Andrew Beckett

1 replies • 7805 views
Discussion

Transfering a vector output of one test to another test in Assembler

Category: Custom IC Design

By baltacican

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updated over 3 years ago by Andrew Beckett

3 replies • 10372 views
Discussion

Does ADE license is necessary for export hspice netlist in virtuoso?

Category: Custom IC Design

By lightyear

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updated over 3 years ago by Andrew Beckett

1 replies • 9038 views
Discussion

How to find quickly the instances with largest current?

Category: Custom IC Design

By StephanWeber

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started over 3 years ago

0 replies • 7627 views
Discussion

How to know the maximum Vds and Vgd voltage

Category: Custom IC Design

By Detailer

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updated over 3 years ago by FormerMember

1 replies • 9175 views
Discussion

Referencing a design variable to another - ADE Assembler

Category: Custom IC Design

By EmJay

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updated over 3 years ago by StephanWeber

4 replies • 3118 views
Discussion

How to get statistical corner by seed and run id in sigma-scaled sampling?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

2 replies • 8921 views
Discussion

A general question about warnings and notices in Virtuoso

Category: Custom IC Design

By MohNaj

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updated over 3 years ago by FormerMember

1 replies • 11517 views
Discussion

How to have a scs file using a design variable or relative path

Category: Custom IC Design

By Pedro P

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updated over 3 years ago by Andrew Beckett

1 replies • 8209 views

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