Custom IC Design

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Noise Summary per Instance

Category: Custom IC Design

By illaoi

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updated over 2 years ago by Andrew Beckett

5 replies • 8169 views
Discussion

NO DC solution found(No convergence) when use ADEXL,but use ADEL is right.

Category: Custom IC Design

By SpiceHusky

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updated over 2 years ago by Andrew Beckett

3 replies • 1952 views
Discussion

Spectre warning: there are some nodes and instances from the netlist topology check.

Category: Custom IC Design

By ppptt

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updated over 2 years ago by Andrew Beckett

1 replies • 6799 views
Discussion

PVS fails with version `GLIBCXX_3.4.26' not found

Category: Custom IC Design

By thspaet

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updated over 2 years ago by thspaet

3 replies • 3126 views
Discussion

setting cell's view in config as dynamic parameter

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by sjwprcker

2 replies • 1354 views
Discussion

BJT models HiCUM (bht)

Category: Custom IC Design

By sidm

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updated over 2 years ago by sidm

6 replies • 7986 views
Discussion

DRC check and LVS check has no error but still seeing the layer error?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Andrew Beckett

1 replies • 6091 views
Discussion

Setting dynamic parmeter in pss analysis

Category: Custom IC Design

By Abhrarup

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updated over 2 years ago by Andrew Beckett

1 replies • 6193 views
Discussion

Maestro : Width of columns in "Results" Tab is large. How to reduce it?

Category: Custom IC Design

By Saikiran IND

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updated over 2 years ago by Saikiran IND

2 replies • 1472 views
Discussion

Maestro: Simulation Settings as Output Expressions

Category: Custom IC Design

By Saikiran IND

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updated over 2 years ago by Saikiran IND

2 replies • 6788 views
Discussion

The region of operation of MOS transistor

Category: Custom IC Design

By PhD Student

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updated over 2 years ago by PhD Student

12 replies • 13460 views
Discussion

Simulation startup is too slow

Category: Custom IC Design

By Firdos

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updated over 2 years ago by ShawnLogan

1 replies • 6550 views
Discussion

rexMatchp error when netlist

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by Andrew Beckett

1 replies • 6578 views
Discussion

Ramp signal generator in Verilog-A

Category: Custom IC Design

By delgsy

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updated over 2 years ago by ShawnLogan

1 replies • 9298 views
Discussion

Post Trimming Simulation for Oscillator Circuit

Category: Custom IC Design

By yoshi777

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updated over 2 years ago by ShawnLogan

8 replies • 10551 views

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