Custom IC Design

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Discussion

Clarification on Simulation Failures with Max. Jobs > 1 in ADE Assembler

Category: Custom IC Design

By baltaci
•
started 9 months ago

0 replies • 724 views
Discussion

How to run Assura Open Run from the command line?

Category: Custom IC Design

By LoVyacheslavvVEMs
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started 9 months ago

0 replies • 1990 views
Discussion

Clicking Check and Save in Verilog Editor of Virtuoso returns error 'Extract Failed for Cellview"

Category: Custom IC Design

By DK202409295316
•
started 9 months ago

0 replies • 1243 views
Discussion

Celsius CFD Crashing after clicking simulation button

Category: Custom IC Design

By HSDROP
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started 9 months ago

0 replies • 1935 views
Discussion

How to Set Up a Config View to Easily Switch Between Schematic and Calibre of DUT for Multiple Testbenches?

Category: Custom IC Design

By Meraj Ahmad
•
updated 9 months ago by Meraj Ahmad

2 replies • 3565 views
Discussion

AMS simvision cannot load big psf.trn

Category: Custom IC Design

By gkasap92
•
started 9 months ago

0 replies • 2076 views
Discussion

Force virtuoso (Layout XL) to NOT create warning markers in design

Category: Custom IC Design

By CSCNalu
•
updated 9 months ago by RobMan

2 replies • 3188 views
Discussion

Characterization of Full adder that use transmission gates using liberate

Category: Custom IC Design

By TM20240913386
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updated 9 months ago by TM20240913386

1 replies • 2489 views
Discussion

error when generating snp files from a variable

Category: Custom IC Design

By TommasoF
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updated 9 months ago by TommasoF

3 replies • 2685 views
Discussion

ddt VerilogA usage

Category: Custom IC Design

By AndreaD
•
started 9 months ago

0 replies • 2292 views
Discussion

Display Resource Editor: Different Colors for Schematic and Layout Axis

Category: Custom IC Design

By sgcad
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updated 10 months ago by sgcad

3 replies • 3322 views
Discussion

Quantus not running an returning error with no description

Category: Custom IC Design

By Awab
•
updated 10 months ago by ConradJ

1 replies • 3366 views
Discussion

How to get maximum value of s11 Trace

Category: Custom IC Design

By NS202408066722
•
updated 10 months ago by NS202408066722

2 replies • 2466 views
Discussion

Author and library name in sheet border

Category: Custom IC Design

By DomiHammerfall
•
updated 10 months ago by DomiHammerfall

2 replies • 2823 views
Discussion

Error using probe terminal for dspf stb analysis

Category: Custom IC Design

By unSkilled
•
updated 10 months ago by Andrew Beckett

1 replies • 2993 views

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