Custom IC Design

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Discussion

use cadence liberate to characterize a cell that has capacitance and resistance,but failed...

Category: Custom IC Design

By TH20240830782

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updated over 1 year ago by TH20240830782

2 replies • 1329 views
Discussion

regarding simulating a verilogams file in cadence for implementing mtj

Category: Custom IC Design

By JJ202409288946

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updated over 1 year ago by JJ202409288946

2 replies • 3540 views
Discussion

Virtuoso_'Analog_Design_Environment_L', 'Analog_Design_Environment_XL', and 'Analog_Design_Environment_L' License Checkout Failure IC 6.1.8

Category: Custom IC Design

By SA202410022720

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updated over 1 year ago by Andrew Beckett

1 replies • 672 views
Discussion

Select Multiple Traces by Corner in ViVa

Category: Custom IC Design

By KTBuckON

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updated over 1 year ago by KTBuckON

2 replies • 3302 views
Discussion

Feed results of AC analysis back to TRAN analysis (Spectre)

Category: Custom IC Design

By mikewu999

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started over 1 year ago

0 replies • 2788 views
Discussion

Warning (CMI-2477) Rds is less then 0.001 gpdk90nm

Category: Custom IC Design

By AL202409293035

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updated over 1 year ago by AL202409293035

2 replies • 3575 views
Discussion

Exporting GDS with groups intact layout

Category: Custom IC Design

By gkasap92

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updated over 1 year ago by Andrew Beckett

1 replies • 3119 views
Discussion

Regarding Code to Generate Analog Matching Set Pattern

Category: Custom IC Design

By NG202409204827

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updated over 1 year ago by Andrew Beckett

3 replies • 3337 views
Discussion

Combine only selected analog traces instead of all analog traces

Category: Custom IC Design

By HYKen

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updated over 1 year ago by Andrew Beckett

1 replies • 2844 views
Discussion

stb Results Documentation

Category: Custom IC Design

By Analog Pete

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updated over 1 year ago by Andrew Beckett

1 replies • 3253 views
Discussion

modgen issue (layout flipping horizontally/vertically)

Category: Custom IC Design

By supriyo1985

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started over 1 year ago

0 replies • 564 views
Discussion

Fatal error during callibre view

Category: Custom IC Design

By rtyuy

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updated over 1 year ago by Andrew Beckett

1 replies • 2983 views
Discussion

Deep Nwell in gpdk180nm

Category: Custom IC Design

By Sameerpy

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started over 1 year ago

0 replies • 2826 views
Discussion

Failed to initialize incremental netlisting

Category: Custom IC Design

By sjwprc

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updated over 1 year ago by Andrew Beckett

3 replies • 21645 views
Discussion

Not able to start XRUN (Error: No such file or directory)

Category: Custom IC Design

By MT202407295352

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updated over 1 year ago by MT202407295352

2 replies • 4693 views

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