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Custom IC Design

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  • Discussion

    Celsius CFD Crashing after clicking simulation button

    Category: Custom IC Design

    By HSDROP HSDROP

    •

    started 9 months ago

    0 replies • 1925 views
  • Discussion

    How to Set Up a Config View to Easily Switch Between Schematic and Calibre of DUT for Multiple Testbenches?

    Category: Custom IC Design

    By Meraj Ahmad Meraj Ahmad

    •

    updated 9 months ago by Meraj Ahmad

    2 replies • 3543 views
  • Discussion

    AMS simvision cannot load big psf.trn

    Category: Custom IC Design

    By gkasap92 gkasap92

    •

    started 9 months ago

    0 replies • 2065 views
  • Discussion

    Force virtuoso (Layout XL) to NOT create warning markers in design

    Category: Custom IC Design

    By CSCNalu CSCNalu

    •

    updated 9 months ago by RobMan

    2 replies • 3174 views
  • Discussion

    Characterization of Full adder that use transmission gates using liberate

    Category: Custom IC Design

    By TM20240913386 TM20240913386

    •

    updated 9 months ago by TM20240913386

    1 replies • 2477 views
  • Discussion

    error when generating snp files from a variable

    Category: Custom IC Design

    By TommasoF TommasoF

    •

    updated 9 months ago by TommasoF

    3 replies • 2668 views
  • Discussion

    ddt VerilogA usage

    Category: Custom IC Design

    By AndreaD AndreaD

    •

    started 9 months ago

    0 replies • 2281 views
  • Discussion

    Display Resource Editor: Different Colors for Schematic and Layout Axis

    Category: Custom IC Design

    By sgcad sgcad

    •

    updated 9 months ago by sgcad

    3 replies • 3309 views
  • Discussion

    Quantus not running an returning error with no description

    Category: Custom IC Design

    By Awab Awab

    •

    updated 10 months ago by ConradJ

    1 replies • 3339 views
  • Discussion

    How to get maximum value of s11 Trace

    Category: Custom IC Design

    By NS202408066722 NS202408066722

    •

    updated 10 months ago by NS202408066722

    2 replies • 2450 views
  • Discussion

    Author and library name in sheet border

    Category: Custom IC Design

    By DomiHammerfall DomiHammerfall

    •

    updated 10 months ago by DomiHammerfall

    2 replies • 2809 views
  • Discussion

    Error using probe terminal for dspf stb analysis

    Category: Custom IC Design

    By unSkilled unSkilled

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 2978 views
  • Discussion

    Change code in veriloga view from external program

    Category: Custom IC Design

    By mikewu999 mikewu999

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 2390 views
  • Discussion

    Verilog-A: Can I ignore WARNING (VACOMP-1047)

    Category: Custom IC Design

    By mikewu999 mikewu999

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 2564 views
  • Discussion

    Transient Simulation waveform abnormal

    Category: Custom IC Design

    By SkkyLee SkkyLee

    •

    updated 10 months ago by hayess

    1 replies • 2446 views
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