Custom IC Design

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Discussion

How to Toggle Metal Layer Visibility Sequentially with Bindkeys?

Category: Custom IC Design

By SS202502085313

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updated 8 months ago by Andrew Beckett

3 replies • 2685 views
Discussion

Control position of instance placement in an ihdl imported schematic

Category: Custom IC Design

By mrharris

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updated 8 months ago by Andrew Beckett

1 replies • 2069 views
Discussion

Finding EAD/ICT file for running parasitic Extraction in Virtuoso EXL

Category: Custom IC Design

By AL202502074331

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updated 8 months ago by Andrew Beckett

1 replies • 652 views
Discussion

Y-axis units and labels when plotting from ADE

Category: Custom IC Design

By mikewu999

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updated 8 months ago by Andrew Beckett

2 replies • 2417 views
Discussion

Back and forward history buttons in Schematic Editor clearing probed nets?

Category: Custom IC Design

By ES20241003727

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updated 8 months ago by Andrew Beckett

2 replies • 2200 views
Discussion

Enabling disk-space-check via .cdsinit

Category: Custom IC Design

By HoWei

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started 8 months ago

0 replies • 1880 views
Discussion

Installscape issue on Rocky linux8/9 and Almalinux 9

Category: Custom IC Design

By CB202409064221

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updated 9 months ago by CB202409064221

3 replies • 1674 views
Discussion

Virtuoso Schematic shows graphically different values than query

Category: Custom IC Design

By WRM

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updated 9 months ago by WRM

2 replies • 2361 views
Discussion

Unable to remove text labels after flattening layout pcell

Category: Custom IC Design

By Ma100B

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updated 9 months ago by Ma100B

5 replies • 2965 views
Discussion

Maestro - problem with sweeping a transistor parameter because of netlist format

Category: Custom IC Design

By frankp

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updated 9 months ago by frankp

2 replies • 809 views
Discussion

Skill function to set x- or y-axis to linear scale

Category: Custom IC Design

By TB202408221839

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started 9 months ago

0 replies • 393 views
Discussion

Merge buses when creating a symbol from SpectreText netlist

Category: Custom IC Design

By ArthurP

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started 9 months ago

0 replies • 2027 views
Discussion

Can move component only up/down or left/right in Cadence Virtuoso

Category: Custom IC Design

By NN202501183253

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updated 9 months ago by RobMan

1 replies • 883 views
Discussion

analogLib/bsource component with complex coefficient

Category: Custom IC Design

By TommasoF

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updated 9 months ago by TommasoF

3 replies • 932 views
Discussion

Is it possible to access design variable as parameter of systemverilog bloc

Category: Custom IC Design

By Mathieu Chene

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started 9 months ago

0 replies • 1996 views

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