Custom IC Design

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Parasitic extraction tools for Cadence

Category: Custom IC Design

By omiya

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updated over 3 years ago by omiya

2 replies • 12304 views
Discussion

how to add printf statement to .cdsenv file?

Category: Custom IC Design

By KurtKimber1

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updated over 3 years ago by KurtKimber1

4 replies • 10421 views
Discussion

Print Noise summary and corresponding OCEAN noiseSummary

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by AncisMichele

15 replies • 16310 views
Discussion

Can the stb simulation in Spectre calculate the negative phase margin?

Category: Custom IC Design

By zuiying

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updated over 3 years ago by zuiying

11 replies • 18339 views
Discussion

Several problems with interfacing Spectre through Matlab

Category: Custom IC Design

By FormerMember

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updated over 4 years ago by Andrew Beckett

1 replies • 5107 views
Discussion

Prevent Maestro from reporting undefined design variables

Category: Custom IC Design

By FormerMember

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updated over 4 years ago by FormerMember

3 replies • 4872 views
Discussion

5G signal sources and simulation inside Spectre / Virtuoso

Category: Custom IC Design

By sidm

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updated over 4 years ago by Andrew Beckett

11 replies • 15177 views
Discussion

DRC Error Using Assura

Category: Custom IC Design

By omiya

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updated over 4 years ago by Andrew Beckett

3 replies • 12047 views
Discussion

global pins

Category: Custom IC Design

By abdurrahman0234

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started over 4 years ago

0 replies • 9139 views
Discussion

Are there any rules and techniques for setting the accuracy and step length when performing transient simulation of unstable systems (that is, the transfer function has RHP) in Spectre?

Category: Custom IC Design

By zuiying

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updated over 4 years ago by zuiying

2 replies • 12617 views
Discussion

Spectre gives different DC simulation results for the same circuit (even some results don't satisfy KCL)

Category: Custom IC Design

By zuiying

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updated over 4 years ago by zuiying

2 replies • 3179 views
Discussion

DC Annotation works sometimes and does not other times

Category: Custom IC Design

By greywanderer

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updated over 4 years ago by greywanderer

4 replies • 11307 views
Discussion

Virtuoso layout hierarchical copy contains mysterious residue from other libraries

Category: Custom IC Design

By chenyanw

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updated over 4 years ago by chenyanw

7 replies • 13064 views
Discussion

skip=cut inst=[...] statements being ignored

Category: Custom IC Design

By wignesb

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updated over 4 years ago by Andrew Beckett

3 replies • 1777 views
Discussion

Virtuoso Error

Category: Custom IC Design

By omiya

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updated over 4 years ago by Andrew Beckett

6 replies • 12394 views

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