Custom IC Design

Latest Posts

Discussion

how to reduce power in post layout simulation

Category: Custom IC Design

By jayakandpal

$usertype
•
started over 7 years ago

0 replies • 13224 views
Discussion

Pin mismatch between Symbols and Schematics

Category: Custom IC Design

By anurans

$usertype
•
updated over 7 years ago by Quek

1 replies • 16379 views
Discussion

Characterizing cells with verilog-A models for components

Category: Custom IC Design

By farhan89

$usertype
•
started over 7 years ago

0 replies • 13839 views
Discussion

Changing the number of series instances in a schematic

Category: Custom IC Design

By MoHas

$usertype
•
updated over 7 years ago by MoHas

9 replies • 23330 views
Discussion

Voltus: how to generate the "DFII Layer Map File"?

Category: Custom IC Design

By dontpanic

$usertype
•
updated over 7 years ago by Saloni Chhabra

6 replies • 8740 views
Discussion

avoiding ams re-gen and re-compile the netlist database

Category: Custom IC Design

By DavidLou

$usertype
•
updated over 7 years ago by DavidLou

2 replies • 14481 views
Discussion

Stream out GDS excluding selected cells

Category: Custom IC Design

By Cambridge Lv

$usertype
•
updated over 7 years ago by Cambridge Lv

2 replies • 2054 views
Discussion

changing the location of netlist creation in loop

Category: Custom IC Design

By Suryansh Singh

$usertype
•
updated over 7 years ago by Suryansh Singh

2 replies • 13611 views
Discussion

Multiple GND PAD/Pins connected to the same GND Plane

Category: Custom IC Design

By PatORiordan

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 2021 views
Discussion

pspice code in spectre.

Category: Custom IC Design

By thomas101

$usertype
•
updated over 7 years ago by thomas101

4 replies • 16977 views
Discussion

Saving ADEXL Results automatically

Category: Custom IC Design

By Michele Ancis

$usertype
•
updated over 7 years ago by Andrew Beckett

13 replies • 28445 views
Discussion

ADE XL corner test error

Category: Custom IC Design

By SteffenK

$usertype
•
updated over 7 years ago by SteffenK

8 replies • 17758 views
Discussion

ideal integrator freq response dc gain problem

Category: Custom IC Design

By sjwprc

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 14332 views
Discussion

regarding to gpdk 45nm

Category: Custom IC Design

By jayakandpal

$usertype
•
started over 7 years ago

0 replies • 16951 views
Discussion

ultrasim netlist stitching

Category: Custom IC Design

By KOTB

$usertype
•
updated over 7 years ago by Andrew Beckett

5 replies • 14410 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.