Custom IC Design

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Discussion

Extracted Netlist Simulation Speedup?

Category: Custom IC Design

By MMueller

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updated over 8 years ago by Andrew Beckett

2 replies • 13784 views
Discussion

VHDL-AMS simulation issue

Category: Custom IC Design

By srana01

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started over 8 years ago

0 replies • 14996 views
Discussion

ADE/Spectre Name Mapping with Extracted Views

Category: Custom IC Design

By BrJaWr

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started over 8 years ago

0 replies • 634 views
Discussion

xmax and xmin are returning nil

Category: Custom IC Design

By asetji

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updated over 8 years ago by asetji

2 replies • 14877 views
Discussion

How can I use a vpwlf source with design variable for filename in AMS simulator (with UNL)?

Category: Custom IC Design

By mad monster

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updated over 8 years ago by mad monster

1 replies • 6948 views
Discussion

Printing Corner Analysis information using VerilogA module

Category: Custom IC Design

By ashrafSazid

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started over 8 years ago

0 replies • 12826 views
Discussion

Hierarchy Editor: Instance bindings @ 2nd level of hierarchy depth

Category: Custom IC Design

By PNadeau

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updated over 8 years ago by PNadeau

2 replies • 14836 views
Discussion

Automatic naming of ADEXL history items

Category: Custom IC Design

By PNadeau

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started over 8 years ago

0 replies • 13978 views
Discussion

MATLAB crashing with SpectreRF Toolbox

Category: Custom IC Design

By doorscops

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updated over 8 years ago by lekez2005

5 replies • 14939 views
Discussion

[URI] Issues usign the scaleparam function in the URI (Unified Reliability Interface) with multiple aging models.

Category: Custom IC Design

By FAVG

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updated over 8 years ago by Andrew Beckett

1 replies • 13752 views
Discussion

Reg channel length in gpdk045

Category: Custom IC Design

By Pasupathy KR

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started over 8 years ago

0 replies • 13272 views
Discussion

Modifying extracted netlist for post layout simulation

Category: Custom IC Design

By Hasan91

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started over 8 years ago

0 replies • 13468 views
Discussion

Problem in QRC Extraction due to inconsistent models

Category: Custom IC Design

By Casp

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updated over 8 years ago by DeepAG

3 replies • 13615 views
Discussion

Floorplanner generate physical hierarchy

Category: Custom IC Design

By RVERP

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started over 8 years ago

0 replies • 13223 views
Discussion

[ADE XL] Compiling verilog-A module

Category: Custom IC Design

By Seokhyun Jeong

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started over 8 years ago

0 replies • 13787 views

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