Designing for low-power

Hi,

Yes Indeed power is a cosideration now.(<130 nm regime).
In my project I use Clock_gating to reduce Dynamic power.
Leakage no presription.

If possible Can u let us know about the Power considerations with changing Technologies and their dependencies(esp 65 nm)


Ranga

Ranga,

As you move to 65 nm technology, you will see a huge increase in leakage power. Power shut off (PSO) is emerging as a common method for controlling leakage power. You simply turn off the blocks that are not being used so they don't dissipate leakage power. For example, if you are listening to music on a video iPod, the video processing circuits are not used and can be turned off to reduce leakage power.

Supply voltage is another thing to consider. Both dynamic and leakage power are directly proportional to voltage. Many designs are using Multiple Supply Voltage (MSV). For lower performance blocks, you can use a lower supply voltage for power reduction. For higher performance blocks, you can use a higher supply voltage for performance improvement.

Some really advanced designs use Dynamic Voltage, Frequency Scaling (DVFS). Here, you dynamically adjust the supply voltage to match the performance required. When you need high performance, you can crank up the voltage to speed up the circuits. When you don't need high performance, you can drop the voltage to save power.

While these design techniques reduce power dissipation, they come at a cost of increased design complexity. The Common Power Format (CPF) and Cadence's low-power solution have been designed to manage this design complexity (and risk). Please visit http://www.cadence.com/lowpower/ for more details.

Luke