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  3. Designing for low-power

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Designing for low-power

archive
archive over 18 years ago
Hi All,

Well, it's a bit quiet in here, so I'll post and see if I can stimulate something here.

Before I start, I’d like to say that folks shouldn’t feel restricted to just discussing Cadence tools or issues with them in here. This is a low-power forum, and I’d like to see some discussion and debate on techniques and ideas just as much as seeing posts about specific tools (ie anything goes, as long as it is roughly on-topic).

So, designing for low-power:

Is power a consideration?

What do you, as a designer, do to limit static (leakage) or dynamic power?

How does power rate in the “traditional” trade-offs of Area, Speed and Tape-out date?

Does your management understand power is an issue to you?

I’ll see if this gets a few replies before I give my own answers.


Chris


Originally posted in cdnusers.org by Chris_Byham
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  • archive
    archive over 18 years ago

    Hi,

    Yes Indeed power is a cosideration now.(<130 nm regime).
    In my project I use Clock_gating to reduce Dynamic power.
    Leakage no presription.

    If possible Can u let us know about the Power considerations with changing Technologies and their dependencies(esp 65 nm)


    Ranga


    Originally posted in cdnusers.org by ranga
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  • archive
    archive over 18 years ago

    Hi,

    Yes Indeed power is a cosideration now.(<130 nm regime).
    In my project I use Clock_gating to reduce Dynamic power.
    Leakage no presription.

    If possible Can u let us know about the Power considerations with changing Technologies and their dependencies(esp 65 nm)


    Ranga


    Originally posted in cdnusers.org by ranga
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