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How to stream in Verilog to Virtuoso using "Retain reference library (No Merge)"

naderi

Hello All,

 Is there any option like "Retain Refrence Library (No Merge)" to stream in Verilog codes into Cadence-Virtuoso using refrence library cells?

I have a large design synthesized and P&R by BuildGates and Encounter. Now I Need to import the GDSII and Verilog file into Cadence for LVS, DRC and Postlayout simulation. For GDSII, the "Retain Refrence Library (No Merge)" option uses library cells instead of making new cells in target library, which reduces disk usage. But it seems verilog-impoter does not have such an option. How to stream in Verilog to Virtuoso using refrence library cells?

Thanks,

Ali

  •  In IC5141, in the Tools->Import->verilog form is a 'reference library' entry  (3. from the top), that has per default the basic and sample included. Does that not work ?

  • Not for this purpose. All reference libs that were used for synthesis, should be given there for creating schematic view and verilog definitions. Indeed, the importer makes a new copy of them in the target lib that comsumes a lot of time and disk space.

    Regrads,

    Ali 

     

  • Hi Ali,
     
    This question is a little out of my area of expertise, so I asked a colleague for help on your question.  I'll pass along that information below.  You might want to try posting this inquiry under the "Custom IC Design" area- there are probably more Virtuoso users there.
     
    Thanks,
    Bob
     
     
    It would be useful to know which version of Virtuoso is being referenced.
    ihdl uses ref_lib_list in the parmFile while the Verilog Import form in IC 5.1.41
    has a line for Reference Libraries to be specified.
     
    From the product documentation for Verilog Import:

    Reference Libraries

    Refers to the libraries that contain Design Framework II reference cells. Typically, these reference cells are imported as part of another design or are ASIC library cells. If a cell exists in a reference library with the same name as the module to import, Verilog In does not import the module. If you want to generate a multisheet schematic, you must specify a reference library containing sheet border and index sheet symbols (for example, the US_8ths library provided by Cadence). The default reference libraries are sample and basic.

    For incomplete designs, if the description of a module is not provided, but a symbol for the module exists in the reference library, it is used to create a structural view for the instantiating module(s). For more details of symbol selection, refer to the section Using Reference Libraries to Import Incomplete Designs.

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