How to stream in Verilog to Virtuoso using "Retain reference library (No Merge)"

Hello All,

 Is there any option like "Retain Refrence Library (No Merge)" to stream in Verilog codes into Cadence-Virtuoso using refrence library cells?

I have a large design synthesized and P&R by BuildGates and Encounter. Now I Need to import the GDSII and Verilog file into Cadence for LVS, DRC and Postlayout simulation. For GDSII, the "Retain Refrence Library (No Merge)" option uses library cells instead of making new cells in target library, which reduces disk usage. But it seems verilog-impoter does not have such an option. How to stream in Verilog to Virtuoso using refrence library cells?

Thanks,

Ali