error after CTS: ERROR:TCLCMD-917

 Hi Prashant,

There is definitely something FE doesn't like about the constraints. Look at one of the line numbers it complains about in top_asic.pt and see if you can tell what it is. I know you have verified that your pins exist, but maybe the way the line in the constraints is looking for them is what's not working. You can try entering the particular line at the command prompt and see if you get any info back which explains the problem more.

- Kari 

Hi Kari,

Thanks for the reply.

I have checked manually entering commands from "top_asic.pt" file, then i found for only on ecommand it is showing error and that command is

 encounter 2> set_max_time_borrow  0 [get_ports {EEPROM_DO_eep2[59]}]
**ERROR: (TCLCMD-917):  Cannot find 'clocks, pins, or instances' that match 'EEPROM_DO_eep2[59]'

i have got this type of error for all ports(400 ports).

Please suggest 

Can you try escaping the brackets?

Hi Kari,

Thanks for the reply.  I tride with escaping or removing the brackets but still it is showing the same error.

As i have written erliar also, i can see physical layout of the pins or ports and completed nanoroute also.

does this error effects to the design? if yes what parameter it effects??

I have seen constraint (SDC) file but this caommand is not there, from which file tool writes or takes this command and  what is  usage or application of this command??  

I have cleaned the timing (violation free) and DRC also.  

Thanks & Regards,

Kul 

set_max_time_borrow only apply to "clocks, latch cells, data pins or clock pins" not on a "port".

li siang

Hi li siang,

 thanks for reply. here i am working on subchip (block level) design, all ports are nothing but pins. so i have 400 pins and i am getting same error for all. if it is not applied to port, is the command syntax problem or any other problem?

from which input, tool is dumping this command in "top_asic.pt" file (i found command in this fil) or any other related command in SDC file ?

Thanks & Regards,

Kul 

So you have a latch based I/O block level design.  Not sure how you got the SDC file generated on the I/O ports.  You can work around this problem by tracing the I/O port to the first latch and apply the set_max_tim_borrow on the latch instance since the instance name should not change from version to version (after re-synthesis).

li siang

NAME

SYNTAX

object_list

ARGUMENTS

 Hi lisiang,

my design is not latch based but iave around 13 latches in the design. I have seen while writing (saving) the CTS database, it is writing out the "top_asic.pt" file and i saw some warnings while saving the database.

 encounter 13> savedesign design_db/cts_top_asic.enc
Redoing specifyClockTree  -clkfile new_Clock.ctstch  ...
Writing Netlist "design_db/cts_top_asic.enc.dat/top_asic.v" ...
Calling write_sdc ...
**WARN: (ASRT-310):     Synopsys SDC does not support set_fanout_load on input ports
Saving clock tree spec file 'design_db/cts_top_asic.enc.dat/top_asic.ctstch' ...
Saving configuration ...
Saving preference file design_db/cts_top_asic.enc.dat/enc.pref.tcl ...
*Info: All current timing derate settings are set to default value of 1.0.
Saving SI fix option to 'design_db/cts_top_asic.enc.dat/siFix.option'...
Saving floorplan ...
Saving Drc markers ...
Saving placement ...
*** Completed savePlace (cpu=0:00:00.0 real=0:00:01.0 mem=285.1M) ***
Saving route ...
*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=285.1M) ***
*** Completed saveYieldMap (cpu=: 0:00:00.0 real=0:00:00.0 mem=: 0.000M) ***
Creating constraint file...

 1. due to above warning is it creating any problem??

2. In the CTS. cts mode setup we have option for CTS TRACE "Balance non-clock pins" and i have not enabled any one of the option (1. data pins of flipflop/latches 2. I/O pins), i am confused to use these option so i have not enabled, due to this any change happens??

 Regards,

 Prashant

 if your block is not a latch based design then you should not have the max_time_borrow in your orignal sdc file ( i assumed the latches you mentioned are used as a lockup latch for scan path).  The error/warning should not matter.

li siang

 Hi li siang,

 we have used latches for the scan path only. in the original SDC fil, i have not set this command but tool is generating new sdc file (top_asic.pt) while dumping the cts database and next onwards it is taking same sdc file. if i remove the "top_asic.pt" file path from the config file and load the database then i will not get any errors.

thanks for all responses.

Regards,

Prashant