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error after CTS: ERROR:TCLCMD-917

kulprashant

 Hi,

when i read the CTS databese or routed dababase in the encounter, it shows following type of error:

 
**ERROR: (TCLCMD-917):    Cannot find 'clocks, pins, or instances' that match 'ADC_StartConv_DFT_IO' (File /projects/es202b/es202-000/RevA/local/layout/encounter/run.Tata_Netlist_Rev12/new_design/encounter/18Aug_trial/design_db/cts_top_asic.enc.dat/top_asic.pt, Line 2789).

**ERROR: (TCLCMD-917):    Cannot find 'clocks, pins, or instances' that match 'EEPROM_R_eep0' (File /projects/es202b/es202-000/RevA/local/layout/encounter/run.Tata_Netlist_Rev12/new_design/encounter/18Aug_trial/design_db/cts_top_asic.enc.dat/top_asic.pt, Line 4204).

**ERROR: (TCLCMD-917):    Cannot find 'clocks, pins, or instances' that match 'EEPROM_R_eep1' (File /projects/es202b/es202-000/RevA/local/layout/encounter/run.Tata_Netlist_Rev12/new_design/encounter/18Aug_trial/design_db/cts_top_asic.enc.dat/top_asic.pt, Line 4215).

1. i can see this error for all pins (nearly 400 pins design)

2. when i read the placement database then there will be no such type of error. i took same database did CTS and routing and saved.

3. when i will read this CTS or routind data, i got the errors. then i check my confiig file (for the CTS database .enc.dat/") and removed "top_asic.pt" file and then load the config file there was no such errors and then i laod the constraint file (loadTimingCons top_asic.pt), then i git same error

4. In layout all pins are present (dumped the io file and checked).

 Can anyone suggest me what is the cause for such type of error and what is work around to solve this type of problem.

Regards,

Prashant

 

 

 

 

Parents

  • So you have a latch based I/O block level design.  Not sure how you got the SDC file generated on the I/O ports.  You can work around this problem by tracing the I/O port to the first latch and apply the set_max_tim_borrow on the latch instance since the instance name should not change from version to version (after re-synthesis).

     

    li siang

     

    NAME

    set_max_time_borrow

    Limits time borrowing for latches.

    SYNTAX

    string set_max_time_borrow value

    object_list

    float

    value

    list

    object_list

    ARGUMENTS

    value

    Specifies the value to which the max_time_borrow attribute is set. Defines the desired limit of time borrowing on the latches specified in object_list. delay_value must be between zero and the default maximum derived from the waveform. By default, the maximum is derived from the ideal clock waveform driving each latch, and is equal to (closing_edge - open_edge). Library setup and data-to-Q propagation times are automatically taken into account. delay_value is in the same units as those in the technology library used during analysis.

    object_list

    Specifies a list of objects in the current_design for which time borrowing is to be limited to value. The objects can be clocks, latch cells, data pins, or clock (enable) pins. If a cell is specified, all enable pins on that cell are affected.

Reply

  • So you have a latch based I/O block level design.  Not sure how you got the SDC file generated on the I/O ports.  You can work around this problem by tracing the I/O port to the first latch and apply the set_max_tim_borrow on the latch instance since the instance name should not change from version to version (after re-synthesis).

     

    li siang

     

    NAME

    set_max_time_borrow

    Limits time borrowing for latches.

    SYNTAX

    string set_max_time_borrow value

    object_list

    float

    value

    list

    object_list

    ARGUMENTS

    value

    Specifies the value to which the max_time_borrow attribute is set. Defines the desired limit of time borrowing on the latches specified in object_list. delay_value must be between zero and the default maximum derived from the waveform. By default, the maximum is derived from the ideal clock waveform driving each latch, and is equal to (closing_edge - open_edge). Library setup and data-to-Q propagation times are automatically taken into account. delay_value is in the same units as those in the technology library used during analysis.

    object_list

    Specifies a list of objects in the current_design for which time borrowing is to be limited to value. The objects can be clocks, latch cells, data pins, or clock (enable) pins. If a cell is specified, all enable pins on that cell are affected.

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