Timing constraint files

Hi,

I am working on digital block (subchip) and i have two SDC files ie

1. functional SDC file (which contains constraints, system clock and other generated clocks)

2. scan SDC (which contains constraints and only scan clock defenation)

The difference between these two SDC is:

functional SDC has same constraints (all) as scan SDC, the only difference is scan clock defenation(create_clock scan_clk) is not thier in functional SDC.

here i am get confused: for which SDC file, i have to do P&R and dumped the final routed netlist which goes for top level

i cannot use both the SDC file at the same time and execute the P&R, then how to use this?

I have read in other P&R tool application papers, we can use functional SDC file and at CTS stage scan clock sdc parameters are used for the timing checks or either way.

if any one knows, please suggeest ASAP.

Note: my input verilog netlist is scan-stiched netlist.  

Thanks & Regards,

Kul