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Timing constraint files

kulprashant

Hi,

I am working on digital block (subchip) and i have two SDC files ie

1. functional SDC file (which contains constraints, system clock and other generated clocks)

2. scan SDC (which contains constraints and only scan clock defenation)

The difference between these two SDC is:

functional SDC has same constraints (all) as scan SDC, the only difference is scan clock defenation(create_clock scan_clk) is not thier in functional SDC.

here i am get confused: for which SDC file, i have to do P&R and dumped the final routed netlist which goes for top level

i cannot use both the SDC file at the same time and execute the P&R, then how to use this?

I have read in other P&R tool application papers, we can use functional SDC file and at CTS stage scan clock sdc parameters are used for the timing checks or either way.

if any one knows, please suggeest ASAP.

Note: my input verilog netlist is scan-stiched netlist.  

Thanks & Regards,

Kul 

  •  Hi Kul,

     You can use both SDC files for your flow. This is one use of MMMC (multi-mode, multi-corner). It involves some setup work on your part, but you only have two modes (functional and scan), so it won't be too bad. Look in the user guide for "Performing Multi-Mode Multi-Corner Timing Analysis and Optimization" (chapter 31 in the 7.1 User Guide).

    Have fun, it's pretty cool!

    - Kari 

     

  • Hi Kari,

    Thanks for the reply.

    I am working on VDIO (virtuoso digital imlimentation opt..)tool which built in SoC encounter ver6.2 and i am not sure it will support for MMMC or not.

    i followed the method like this,

    1. i have performed P&R by taking functional SDC upto CTS creation and checked for the timing then unloaded the constraint file using "unloadTimingCon" command and then loaded scan SDC file  and done  the timing checks  and i have not found  any  timing violation  (both for setup  & Hold (i thonk i am lucky or there may be some problem)), then again unloaded the scan SDC file and once again reloaded the functional SDC and cheked for timing  and did CTS optimization and finally routing.

    is this procedure correct???

     2. The whole P&R flow worked on the operating conditions set to Max -- worst (wc) & Min -- best (bc) case and default RC extraction mode (coupled mode).  there no violations after routing.

    To dump the database for STA:

    i have changed extraction mode to "decoupled mode" and oprarting conditions to both max & min to worst case analysis and extracted SPEF file only for worst case analysis and did same change for best case and dumped the best case SPEF (in built extracto, no fire & Ice signoff)

    is it correct way of dumping SPEF file for different case or i have to dump the SPEF with only (wc-bc) combination ???

    STA engineer seeing clock gating violation on best case SPEF file but in encounter it is not showing any violation (not for either case)

    i have checked same path which he got the vioaltions in encounter but it is not showing any violations.

    what may be the cause for this ????

     i checked libraries and there is no problem in library (max-- worst case and min-best cae libs)

    how to dump SPEF files for the worst case and best case mode separately  or any command??

    please suggest.

    Thanks & Regards,

    Kul 

  •  Hi Kul,

    MMMC is available in 6.2, but since you just have the 2 modes, it's easy to stick with what you're doing. The flow you describe is exactly what we did before MMMC (run in functional, then unloadTimingCon, load the scan constraints and check timing, etc.).

    If you want to make sure you're dumping out the right SPEF files, you can load just your WC data into an FE session, output the WC SPEF, then start a new session loading on the BC data and output the BC SPEF. 

    What tool is your STA engineer running? There could be many reasons for him/her to see different timing than what you see, depending on several things. What tool is used for STA, are you both using the same SDC files, etc.

    - Kari 

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