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Timing constraint files

kulprashant

Hi,

I am working on digital block (subchip) and i have two SDC files ie

1. functional SDC file (which contains constraints, system clock and other generated clocks)

2. scan SDC (which contains constraints and only scan clock defenation)

The difference between these two SDC is:

functional SDC has same constraints (all) as scan SDC, the only difference is scan clock defenation(create_clock scan_clk) is not thier in functional SDC.

here i am get confused: for which SDC file, i have to do P&R and dumped the final routed netlist which goes for top level

i cannot use both the SDC file at the same time and execute the P&R, then how to use this?

I have read in other P&R tool application papers, we can use functional SDC file and at CTS stage scan clock sdc parameters are used for the timing checks or either way.

if any one knows, please suggeest ASAP.

Note: my input verilog netlist is scan-stiched netlist.  

Thanks & Regards,

Kul 

Parents

  •  Hi Kul,

    MMMC is available in 6.2, but since you just have the 2 modes, it's easy to stick with what you're doing. The flow you describe is exactly what we did before MMMC (run in functional, then unloadTimingCon, load the scan constraints and check timing, etc.).

    If you want to make sure you're dumping out the right SPEF files, you can load just your WC data into an FE session, output the WC SPEF, then start a new session loading on the BC data and output the BC SPEF. 

    What tool is your STA engineer running? There could be many reasons for him/her to see different timing than what you see, depending on several things. What tool is used for STA, are you both using the same SDC files, etc.

    - Kari 

Reply

  •  Hi Kul,

    MMMC is available in 6.2, but since you just have the 2 modes, it's easy to stick with what you're doing. The flow you describe is exactly what we did before MMMC (run in functional, then unloadTimingCon, load the scan constraints and check timing, etc.).

    If you want to make sure you're dumping out the right SPEF files, you can load just your WC data into an FE session, output the WC SPEF, then start a new session loading on the BC data and output the BC SPEF. 

    What tool is your STA engineer running? There could be many reasons for him/her to see different timing than what you see, depending on several things. What tool is used for STA, are you both using the same SDC files, etc.

    - Kari 

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