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  3. how to reduce power dissipation in deep submicron....

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how to reduce power dissipation in deep submicron....

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archive over 17 years ago

Hi all,

please can anybody give me information about power analysis in the deep submicron technology.


Originally posted in cdnusers.org by mahecadence
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    archive over 17 years ago

    Can you be a bit more specific? What do you mean by "power analysis"? Are you looking for different power reduction techniques, power estimation, etc?

    Luke


    Originally posted in cdnusers.org by lukelang
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    archive over 17 years ago

    Hi lukelang,

    Yes i want to know the power estimation strategy. Please can you clarify this.

    Many thanks in advance.


    Originally posted in cdnusers.org by mahecadence
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    archive over 17 years ago

    RC (RTL Compiler) can estimate power with RTL or synthesized netlist. You can use estimated switching activity or actual switching activity (from VCD, TCF, or SAIF files). In the CPF file, you will specify the power domains (on and off) and supply voltage(s) (which library to use). And yes, you can have different voltages for different blocks. This is known as MSV (Multiple Supply Voltage).

    For what-if analysis, you can code up different CPF files for different power architectures. This will help you determine the optimum power architecture very easily and quickly.

    Since power, timing, and area are all related, RC has the synthesis engine to give you an accurate estimate of all three parameters in one run. After all, it doesn't matter how good the power estimate is if you can't meet timing or exceed your die size.

    You should take a look at Brad Miller's excellent power estimation article at http://www.eetimes.com/news/design/showArticle.jhtml?articleID=201805258 . Please reply if you have any questions.

    Luke


    Originally posted in cdnusers.org by lukelang
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    archive over 17 years ago

    First of all Many thanks lukelang.

    Adding to this i want to know the generalized concept ( if possible any algorithm )for this power reduction in Deep Submicron Technology (not just related to any EDA tool).

    Please can you help me in this.


    Originally posted in cdnusers.org by mahecadence
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    archive over 17 years ago

    If you look inside the .lib file and search for the word "power", you will find parameters for leakage and dynamic power.

    For leakage power, it could be a constant value or a state dependent value. If it is state dependent, then you need to figure out the percentage of time a cell is in each state and ratio the leakage power accordingly.

    For dynamic power, there are lookup tables that determine the power parameters. You provide the toggle frequency and capacitance loading, and RC calculates the power for you. I don't know the algorithm or formula for this calculation.but it is very tedious. You probably don't want to do this by hand.

    Luke


    Originally posted in cdnusers.org by lukelang
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    archive over 17 years ago

    Thanks Luke,
    The info that you are given is very helpful to me.

    Please can you send me the document or pdf regarding RC Extraction and its relation with Fire & Ice tool.

    thanks in advance.


    Originally posted in cdnusers.org by mahecadence
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