Stats

  • Locked Locked
  • Replies 6
  • Subscribers 92
  • Views 17576
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

input for generating SDF

gops
What is the input file for generating SDF?In encounter there is a command writesdf.Is SDF calculated based on extracted RC.I mean SPEF file. Please somebody tell me the exact operation running in tool background when i execute writesdf.

  • Upon importing a design into SoC-Encounter, along with .lib files which describing timing characteristics of cells in the design and cap tables which drive parasitic estimation, the tool can perform delay calculation.  The resulting SDF file can be exported from the tool with the "write_sdf" command.

  • Hi Bob;

    Thanks for the reply.

    I have read that SDF is calculated from SPEF file.

    So while we go for write_sdf , will the tool extract parasitics and create SPEF file ?
  • write_sdf is most typically run after the design has been timed already which is usually performed with the timeDesign super-command: "timeDesign -postRoute [-si]".  Once the design has been timed, and write_sdf is called the delay calculation in-memory will be used to output the SDF file.  I'm not sure right off whether write_sdf would trigger delay calculation if called on a design that wasn't already timed.  To be safe, I'd recommend calling timeDesign prior to write_sdf.
  • Thanks bob; i used to generate sdf file using GUI---- calculate delay.In this TAB the tool just asks for the name of the output file .Can you please tell me what the tool does internally when i generate sdf file thorough GUI.

  •  

    Navid

    BobD said:

    Upon importing a design into SoC-Encounter, along with .lib files which describing timing characteristics of cells in the design and cap tables which drive parasitic estimation, the tool can perform delay calculation.  The resulting SDF file can be exported from the tool with the "write_sdf" command.

     Dear Bob,

     As you mentioned cap tables are needed for parasitic estimations. Also from Encounter User Guide: if cap tables are not provided, Encounter will use rough estimates for parasitics. Now, I have a 65 nm technology that has .lib and .lef files but I don't see any .ict files which are needed for Cap table generation. 

     Am I supposed to make the .ict file myself? Without the cab tables, after extracting RC and calculating delay (sdf) the Encounter timing analysis built-in tool and also PrimeTime (after back-annotating sdf) show  delay values which are way beyond the expected values for this 65 nm technlogy (example: 0.5ns for an inverter). Do you think if I had cab tables, the delay would have been shorter?What you suggest me to do to get reasonable SDF file in this case?

     

    Thank you very much

  •  Navid,

     You *can* make an ict file yourself, but it's not much fun! The foundry should have this file for your process. Sometimes it's in a back-end kit, not the same place as your .lib and .lef file data. So check around or ask the foundry specifically for this file. 

    Just for a sanity check, you can look in the .lib for the inverter and see if 0.5ns is anywhere within the timing tables. I agree that's quite high for 65nm.

    - Kari 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.