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input for generating SDF

gops
What is the input file for generating SDF?In encounter there is a command writesdf.Is SDF calculated based on extracted RC.I mean SPEF file. Please somebody tell me the exact operation running in tool background when i execute writesdf.
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    Navid

    BobD said:

    Upon importing a design into SoC-Encounter, along with .lib files which describing timing characteristics of cells in the design and cap tables which drive parasitic estimation, the tool can perform delay calculation.  The resulting SDF file can be exported from the tool with the "write_sdf" command.

     Dear Bob,

     As you mentioned cap tables are needed for parasitic estimations. Also from Encounter User Guide: if cap tables are not provided, Encounter will use rough estimates for parasitics. Now, I have a 65 nm technology that has .lib and .lef files but I don't see any .ict files which are needed for Cap table generation. 

     Am I supposed to make the .ict file myself? Without the cab tables, after extracting RC and calculating delay (sdf) the Encounter timing analysis built-in tool and also PrimeTime (after back-annotating sdf) show  delay values which are way beyond the expected values for this 65 nm technlogy (example: 0.5ns for an inverter). Do you think if I had cab tables, the delay would have been shorter?What you suggest me to do to get reasonable SDF file in this case?

     

    Thank you very much

Reply

  •  

    Navid

    BobD said:

    Upon importing a design into SoC-Encounter, along with .lib files which describing timing characteristics of cells in the design and cap tables which drive parasitic estimation, the tool can perform delay calculation.  The resulting SDF file can be exported from the tool with the "write_sdf" command.

     Dear Bob,

     As you mentioned cap tables are needed for parasitic estimations. Also from Encounter User Guide: if cap tables are not provided, Encounter will use rough estimates for parasitics. Now, I have a 65 nm technology that has .lib and .lef files but I don't see any .ict files which are needed for Cap table generation. 

     Am I supposed to make the .ict file myself? Without the cab tables, after extracting RC and calculating delay (sdf) the Encounter timing analysis built-in tool and also PrimeTime (after back-annotating sdf) show  delay values which are way beyond the expected values for this 65 nm technlogy (example: 0.5ns for an inverter). Do you think if I had cab tables, the delay would have been shorter?What you suggest me to do to get reasonable SDF file in this case?

     

    Thank you very much

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