Stats

  • Locked Locked
  • Replies 15
  • Subscribers 94
  • Views 26753
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

clock tree synthesis.

gops
How should i manage CTS efficiently. I need to know what all things should be taken care in the clock tree sppecification file for an optimized clock tree. I usually create the .ctsch file from the tool itself. I just used to give the clock buffer and clock inverter foot prints for the purpose. Will this much information create the clock tree in an efficient way? if not please give me some tips to improve my clock tree. thanks gops.
Parents

  •  You're off to a great start. The .ctstch file generated by FE is the easiest thing to start with. Then you may want to customize it by allowing only certain buffers/inverters (as you mentioned), or using a NONDEFAULT rule for routing the clock tree, using different values for insertion delay/skew/transition, etc. The test will be to see how timing looks after your clock trees are in and you have done a postCTS optimization. If you are not meeting timing, is it due to the clock tree? Should some of your clocks be grouped (balanced together)?

    I would recommend using a double-width double-space NONDEFAULT rule if you have the room. This will improve insertion delay and make the clock less vulnerable to noise.  A lot of designers use only inverters to build the tree. This helps with duty cycle. Another common thing is to limit the buffer/inverter list to just 3 or 4 buf/inv sizes. You may have to run CTS a few times with different settings to get the best results. You'll also want to make sure that everything you intend to be a leaf cell is getting reached, and that you exclude anything you don't want a clock tree built to. I believe the .ctstch file is created based on the SDC constraints, but you can't always tell from those what the true intent of the clocking was. 

Reply

  •  You're off to a great start. The .ctstch file generated by FE is the easiest thing to start with. Then you may want to customize it by allowing only certain buffers/inverters (as you mentioned), or using a NONDEFAULT rule for routing the clock tree, using different values for insertion delay/skew/transition, etc. The test will be to see how timing looks after your clock trees are in and you have done a postCTS optimization. If you are not meeting timing, is it due to the clock tree? Should some of your clocks be grouped (balanced together)?

    I would recommend using a double-width double-space NONDEFAULT rule if you have the room. This will improve insertion delay and make the clock less vulnerable to noise.  A lot of designers use only inverters to build the tree. This helps with duty cycle. Another common thing is to limit the buffer/inverter list to just 3 or 4 buf/inv sizes. You may have to run CTS a few times with different settings to get the best results. You'll also want to make sure that everything you intend to be a leaf cell is getting reached, and that you exclude anything you don't want a clock tree built to. I believe the .ctstch file is created based on the SDC constraints, but you can't always tell from those what the true intent of the clocking was. 

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.