clock tree synthesis.

 You're off to a great start. The .ctstch file generated by FE is the easiest thing to start with. Then you may want to customize it by allowing only certain buffers/inverters (as you mentioned), or using a NONDEFAULT rule for routing the clock tree, using different values for insertion delay/skew/transition, etc. The test will be to see how timing looks after your clock trees are in and you have done a postCTS optimization. If you are not meeting timing, is it due to the clock tree? Should some of your clocks be grouped (balanced together)?

I would recommend using a double-width double-space NONDEFAULT rule if you have the room. This will improve insertion delay and make the clock less vulnerable to noise.  A lot of designers use only inverters to build the tree. This helps with duty cycle. Another common thing is to limit the buffer/inverter list to just 3 or 4 buf/inv sizes. You may have to run CTS a few times with different settings to get the best results. You'll also want to make sure that everything you intend to be a leaf cell is getting reached, and that you exclude anything you don't want a clock tree built to. I believe the .ctstch file is created based on the SDC constraints, but you can't always tell from those what the true intent of the clocking was. 

Here's a quick example. Note that I specified a NonDefaultRule called "WideWire". This rule needs to be defined in the tech LEF file first.

You can refer to the User Guide for more information on all the options in the .ctstch file. 

----------------------------------------------------------------- 

 ClkGrp
+clk1
+clk2 

RouteTypeName CLK_ROUTE
TopPreferredLayer 5
BottomPreferredLayer 3
NonDefaultRule WideWire
PreferredExtraSpace 0
End

#------------------------------------------------------------
# Clock Root   : clk1
# Clock Name   : clk1
# Clock Period : 2ns
#------------------------------------------------------------
AutoCTSRootPin clk1
Period         2ns
MaxDelay       2ns
MinDelay       0ns
MaxSkew        150ps
SinkMaxTran    200ps
BufMaxTran     200ps
AddDriverCell  CLKBUFX16
Buffer         CLKINVX8 CLKINVX12 CLKINVX16
NoGating       NO
DetailReport   YES
SetDPinAsSync  YES
SetIoPinAsSync YES
RouteClkNet    YES
RouteType      CLK_ROUTE
END

#------------------------------------------------------------
# Clock Root   : clk2
# Clock Name   : clk2
# Clock Period : 2ns
#------------------------------------------------------------
AutoCTSRootPin clk2
Period         2ns
MaxDelay       2ns
MinDelay       0ns
MaxSkew        150ps
SinkMaxTran    200ps
BufMaxTran     200ps
AddDriverCell  CLKBUFX16
Buffer         CLKINVX8 CLKINVX12 CLKINVX16
NoGating       NO
DetailReport   YES
SetDPinAsSync  YES
SetIoPinAsSync YES
RouteClkNet    YES
RouteType      CLK_ROUTE
END

 Hello Kari,

 I' m using a similar clock specification file:

However, when Im trying to synthesize the tree I'm getting the following error:

 **ERROR: (SOCCK-657):   No cell is specified for clock clk in the clock tree specification file.
**ERROR: (SOCCK-427):   The clock tree specification file contains an error at line 47: End

My design is a simple shift register with 3 FFs, with the clock input named 'clk'. Do you have any idea what the problem might be??

Thanks,

Alex

 Hi Alex,

 Looks like you're missing the "Buffer" line, telling CTS which buffers or inverters to use to build the tree. Add that in and let me know if it fixed the problem.

- Kari

 Hi Kari,

 Thank you very much for your prompt response. Yes, that fixed it! The reason I omitted the 'Buffer' line is because I specified 'OptAddBuffer NO' since I do not want the CTS to insert any buffers in my design. However, it does insert them. How can I avoid this? Also, when the tree is routed (due to the 'RouteClkNet YES'), other nets are also routed. So my other question is: When I do the Nanoroute (after CTS) in order to route nets properly (I need to apply some MATCH constraints) will this affect the quality of the clock tree?

  Thank you again,

 Alex

 Hi Alex,

I'm a bit confused. If you don't want to build a clock tree, why are you running CTS? :-)

The OptAddBuffer line is to control whether or not buffers/inverters are added during an optimization of the tree AFTER it is built.

After your CTS run, the other nets you see routed are probably just trialRoutes. You will still need to route them for real with nanoRoute. You don't have to worry about the clock nets though; after being routed with nano during CTS, they are marked fixed. The more typical problem is having violations when routing the rest of the design because nano really needed to slightly move a clock net in order to connect a signal net. To allow nano to be able to move signal nets, you would do the following before calling routeDesign:

changeUseClockNetStatus -noFixedNetWires

This will allow nanoRoute to move a clock wire if it has to. We have never seen this affect the clock timing.

Since it seems you don't want to build a clock tree (but I may not fully understand your intent), I would suggest just routing your clock nets first with nano:

Hi Kari,

 What I want with my design is a single buffer near the clock input (thus the AddDriverCell line) and after that I need to have only a balanced tree all the way to the leaves (thus the LevelBalanced YES line). Just to give you a better idea of what I'm doing, I've been given a schematic of a design (and its corresponding Verilog netlist) and I was asked to transform this exact design into layout without the addition of any cell that is not already in the schematic. As I mentioned, the schematic has a single specific buffer driving the flops and assumes a balanced tree until the leaves. Sorry for the confusion.

I know that's a weird bit of spec (usually in my designs I dont care about inserted buffers -after all they are there to get the job done), but that's (engineering) life!

Thank you again,

Alex :-)

 I have many doubts and am encountering many situations in the cadence encounter,

first of all i am getting the following error in the clock tree synthesis:

**ERROR: (SOCCK-114): No valid clock tree root specified.

actually i am using a clock for my module. What may i have done  wrong that i got this error?

I have another doubt. as i dont know where to post, i am posting it here in this message itself.

I have a module wherin i am using a ROM from the faraday's memory maker.The memory maker is giving an lef file for the rom we want.

what order should we include the lef files for a 6 metal layer libraries?

 meaning should i include rom.lef  first in the list or last? i hope it is last because the import was done perfectly. I want to know what is the significance of the order of the lef files.

also i encountered another problem because of the rom.lef file.

i dont know the error log number, but it happens during the special route 

it says something like this:

                             Reading LEF technology information...

                                     *ERROR*  "../rom1/rom1.lef", line 44: SITE core not defined at or near "core"

 LEF order: the tech lef needs to be first, then the macro lefs can be read in any order. Make sure the macro lefs do not contain the tech info (metal layer definitions, via definitions, spacing info, etc.)

ROM LEF error: hard to tell what's happening without more info, but it could be that the definition for the SITE called "core" was not read in. But, hard macros like RAMs, ROMs, etc don't need a site to be placed. You can probably comment out the SITE definition from the ROM macro LEF.

clock tree root: I'm assuming this is happening when you try to build the clock tree. Encounter is telling you that no clock root has been defined. Check your .ctstch file (the clock spec file) and make sure the root you're specifying there really exists.