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clock tree synthesis.

gops
How should i manage CTS efficiently. I need to know what all things should be taken care in the clock tree sppecification file for an optimized clock tree. I usually create the .ctsch file from the tool itself. I just used to give the clock buffer and clock inverter foot prints for the purpose. Will this much information create the clock tree in an efficient way? if not please give me some tips to improve my clock tree. thanks gops.
Parents

  •  

     I have many doubts and am encountering many situations in the cadence encounter,

    first of all i am getting the following error in the clock tree synthesis:

     

    **ERROR: (SOCCK-114): No valid clock tree root specified.

    actually i am using a clock for my module. What may i have done  wrong that i got this error?

     

    I have another doubt. as i dont know where to post, i am posting it here in this message itself.

    I have a module wherin i am using a ROM from the faraday's memory maker.The memory maker is giving an lef file for the rom we want.

    what order should we include the lef files for a 6 metal layer libraries?

     meaning should i include rom.lef  first in the list or last? i hope it is last because the import was done perfectly. I want to know what is the significance of the order of the lef files.

     

    also i encountered another problem because of the rom.lef file.

    i dont know the error log number, but it happens during the special route 

    it says something like this:

                                 Reading LEF technology information...

                                         *ERROR*  "../rom1/rom1.lef", line 44: SITE core not defined at or near "core"

Reply

  •  

     I have many doubts and am encountering many situations in the cadence encounter,

    first of all i am getting the following error in the clock tree synthesis:

     

    **ERROR: (SOCCK-114): No valid clock tree root specified.

    actually i am using a clock for my module. What may i have done  wrong that i got this error?

     

    I have another doubt. as i dont know where to post, i am posting it here in this message itself.

    I have a module wherin i am using a ROM from the faraday's memory maker.The memory maker is giving an lef file for the rom we want.

    what order should we include the lef files for a 6 metal layer libraries?

     meaning should i include rom.lef  first in the list or last? i hope it is last because the import was done perfectly. I want to know what is the significance of the order of the lef files.

     

    also i encountered another problem because of the rom.lef file.

    i dont know the error log number, but it happens during the special route 

    it says something like this:

                                 Reading LEF technology information...

                                         *ERROR*  "../rom1/rom1.lef", line 44: SITE core not defined at or near "core"

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