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clock tree synthesis.

gops
How should i manage CTS efficiently. I need to know what all things should be taken care in the clock tree sppecification file for an optimized clock tree. I usually create the .ctsch file from the tool itself. I just used to give the clock buffer and clock inverter foot prints for the purpose. Will this much information create the clock tree in an efficient way? if not please give me some tips to improve my clock tree. thanks gops.
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  •  Hello Kari,

     I' m using a similar clock specification file:

    ClkGroup
          + reset_n
          + clk


    # Sample Route Type Command
    RouteTypeName        CK1
    PreferredExtraSpace    1
    TopPreferredLayer        5
    BottomPreferredLayer     4
    Shielding   VDD VSS
    End

    # Sample Gated CTS Command
     AutoCTSRootPin  clk
     Period            1ns
     MaxDelay      10ps
     MinDelay      0ps
     SinkMaxTran   5ps
     BufMaxTran    5ps
     RootInputTran 5ps    
     MaxSkew           1ps
     LevelBalanced         YES
     NoGating     rising
     MaxDepth      10
     RouteType     CK1
     DetailReport  NO
     RouteClkNet   YES
     PostOpt     YES
     OptAddBuffer  NO
     LeafPin
     + I2/CP rising
     + I0/CP rising
     + I1/CP rising

     AddDriverCell CKBXD8
     End

     

    However, when Im trying to synthesize the tree I'm getting the following error:

     **ERROR: (SOCCK-657):   No cell is specified for clock clk in the clock tree specification file.
    **ERROR: (SOCCK-427):   The clock tree specification file contains an error at line 47: End

     

    My design is a simple shift register with 3 FFs, with the clock input named 'clk'. Do you have any idea what the problem might be??

     

    Thanks,

    Alex

     

     

     

Reply

  •  Hello Kari,

     I' m using a similar clock specification file:

    ClkGroup
          + reset_n
          + clk


    # Sample Route Type Command
    RouteTypeName        CK1
    PreferredExtraSpace    1
    TopPreferredLayer        5
    BottomPreferredLayer     4
    Shielding   VDD VSS
    End

    # Sample Gated CTS Command
     AutoCTSRootPin  clk
     Period            1ns
     MaxDelay      10ps
     MinDelay      0ps
     SinkMaxTran   5ps
     BufMaxTran    5ps
     RootInputTran 5ps    
     MaxSkew           1ps
     LevelBalanced         YES
     NoGating     rising
     MaxDepth      10
     RouteType     CK1
     DetailReport  NO
     RouteClkNet   YES
     PostOpt     YES
     OptAddBuffer  NO
     LeafPin
     + I2/CP rising
     + I0/CP rising
     + I1/CP rising

     AddDriverCell CKBXD8
     End

     

    However, when Im trying to synthesize the tree I'm getting the following error:

     **ERROR: (SOCCK-657):   No cell is specified for clock clk in the clock tree specification file.
    **ERROR: (SOCCK-427):   The clock tree specification file contains an error at line 47: End

     

    My design is a simple shift register with 3 FFs, with the clock input named 'clk'. Do you have any idea what the problem might be??

     

    Thanks,

    Alex

     

     

     

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