clock tree synthesis.

Please clarify the goal of the limitation of the buffer/inverter list? thanks 

The list is required in order to specify the standard cells (inverters/buffers) that the CTS engine will use to create the clock tree. This gives you the opportunity to control which buffers/inverters will be used and therefore affect the quality of the generated clock tree by allowinfg or restricting the use of specific cells. From my experience, using inverters gives a better clock tree in terms of skew and clock insertion delay but you will need to experiment with different options to find the optimum solution.

 Hope this helps,

Alex  

Hello,

How can I generate a useful skew, during CTS, only for particular leafs, for example if early clock is required at clock pin of a memory?

Thank you very much!
Boris.

 Use a Macro Model for the memory clock pins. This is covered in the Clock Tree chapter in the user guide.

Hi Carl

when we use exclude pin we are fixing only data tran and fanout there and no skew. Why do i want to fix tran but no skew ? Pls clarify