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clock tree synthesis.

gops
How should i manage CTS efficiently. I need to know what all things should be taken care in the clock tree sppecification file for an optimized clock tree. I usually create the .ctsch file from the tool itself. I just used to give the clock buffer and clock inverter foot prints for the purpose. Will this much information create the clock tree in an efficient way? if not please give me some tips to improve my clock tree. thanks gops.
Parents

  • Here's a quick example. Note that I specified a NonDefaultRule called "WideWire". This rule needs to be defined in the tech LEF file first.

    You can refer to the User Guide for more information on all the options in the .ctstch file. 

     

    ----------------------------------------------------------------- 

     ClkGrp
    +clk1
    +clk2 

    RouteTypeName CLK_ROUTE
    TopPreferredLayer 5
    BottomPreferredLayer 3
    NonDefaultRule WideWire
    PreferredExtraSpace 0
    End

    #------------------------------------------------------------
    # Clock Root   : clk1
    # Clock Name   : clk1
    # Clock Period : 2ns
    #------------------------------------------------------------
    AutoCTSRootPin clk1
    Period         2ns
    MaxDelay       2ns
    MinDelay       0ns
    MaxSkew        150ps
    SinkMaxTran    200ps
    BufMaxTran     200ps
    AddDriverCell  CLKBUFX16
    Buffer         CLKINVX8 CLKINVX12 CLKINVX16
    NoGating       NO
    DetailReport   YES
    SetDPinAsSync  YES
    SetIoPinAsSync YES
    RouteClkNet    YES
    RouteType      CLK_ROUTE
    END

    #------------------------------------------------------------
    # Clock Root   : clk2
    # Clock Name   : clk2
    # Clock Period : 2ns
    #------------------------------------------------------------
    AutoCTSRootPin clk2
    Period         2ns
    MaxDelay       2ns
    MinDelay       0ns
    MaxSkew        150ps
    SinkMaxTran    200ps
    BufMaxTran     200ps
    AddDriverCell  CLKBUFX16
    Buffer         CLKINVX8 CLKINVX12 CLKINVX16
    NoGating       NO
    DetailReport   YES
    SetDPinAsSync  YES
    SetIoPinAsSync YES
    RouteClkNet    YES
    RouteType      CLK_ROUTE
    END

Reply

  • Here's a quick example. Note that I specified a NonDefaultRule called "WideWire". This rule needs to be defined in the tech LEF file first.

    You can refer to the User Guide for more information on all the options in the .ctstch file. 

     

    ----------------------------------------------------------------- 

     ClkGrp
    +clk1
    +clk2 

    RouteTypeName CLK_ROUTE
    TopPreferredLayer 5
    BottomPreferredLayer 3
    NonDefaultRule WideWire
    PreferredExtraSpace 0
    End

    #------------------------------------------------------------
    # Clock Root   : clk1
    # Clock Name   : clk1
    # Clock Period : 2ns
    #------------------------------------------------------------
    AutoCTSRootPin clk1
    Period         2ns
    MaxDelay       2ns
    MinDelay       0ns
    MaxSkew        150ps
    SinkMaxTran    200ps
    BufMaxTran     200ps
    AddDriverCell  CLKBUFX16
    Buffer         CLKINVX8 CLKINVX12 CLKINVX16
    NoGating       NO
    DetailReport   YES
    SetDPinAsSync  YES
    SetIoPinAsSync YES
    RouteClkNet    YES
    RouteType      CLK_ROUTE
    END

    #------------------------------------------------------------
    # Clock Root   : clk2
    # Clock Name   : clk2
    # Clock Period : 2ns
    #------------------------------------------------------------
    AutoCTSRootPin clk2
    Period         2ns
    MaxDelay       2ns
    MinDelay       0ns
    MaxSkew        150ps
    SinkMaxTran    200ps
    BufMaxTran     200ps
    AddDriverCell  CLKBUFX16
    Buffer         CLKINVX8 CLKINVX12 CLKINVX16
    NoGating       NO
    DetailReport   YES
    SetDPinAsSync  YES
    SetIoPinAsSync YES
    RouteClkNet    YES
    RouteType      CLK_ROUTE
    END

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