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clock tree synthesis.

gops
How should i manage CTS efficiently. I need to know what all things should be taken care in the clock tree sppecification file for an optimized clock tree. I usually create the .ctsch file from the tool itself. I just used to give the clock buffer and clock inverter foot prints for the purpose. Will this much information create the clock tree in an efficient way? if not please give me some tips to improve my clock tree. thanks gops.
Parents

  •  LEF order: the tech lef needs to be first, then the macro lefs can be read in any order. Make sure the macro lefs do not contain the tech info (metal layer definitions, via definitions, spacing info, etc.)

    ROM LEF error: hard to tell what's happening without more info, but it could be that the definition for the SITE called "core" was not read in. But, hard macros like RAMs, ROMs, etc don't need a site to be placed. You can probably comment out the SITE definition from the ROM macro LEF.

    clock tree root: I'm assuming this is happening when you try to build the clock tree. Encounter is telling you that no clock root has been defined. Check your .ctstch file (the clock spec file) and make sure the root you're specifying there really exists.

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  •  LEF order: the tech lef needs to be first, then the macro lefs can be read in any order. Make sure the macro lefs do not contain the tech info (metal layer definitions, via definitions, spacing info, etc.)

    ROM LEF error: hard to tell what's happening without more info, but it could be that the definition for the SITE called "core" was not read in. But, hard macros like RAMs, ROMs, etc don't need a site to be placed. You can probably comment out the SITE definition from the ROM macro LEF.

    clock tree root: I'm assuming this is happening when you try to build the clock tree. Encounter is telling you that no clock root has been defined. Check your .ctstch file (the clock spec file) and make sure the root you're specifying there really exists.

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