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clock tree synthesis.

gops
How should i manage CTS efficiently. I need to know what all things should be taken care in the clock tree sppecification file for an optimized clock tree. I usually create the .ctsch file from the tool itself. I just used to give the clock buffer and clock inverter foot prints for the purpose. Will this much information create the clock tree in an efficient way? if not please give me some tips to improve my clock tree. thanks gops.
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  • Hi Kari,

     What I want with my design is a single buffer near the clock input (thus the AddDriverCell line) and after that I need to have only a balanced tree all the way to the leaves (thus the LevelBalanced YES line). Just to give you a better idea of what I'm doing, I've been given a schematic of a design (and its corresponding Verilog netlist) and I was asked to transform this exact design into layout without the addition of any cell that is not already in the schematic. As I mentioned, the schematic has a single specific buffer driving the flops and assumes a balanced tree until the leaves. Sorry for the confusion.

    I know that's a weird bit of spec (usually in my designs I dont care about inserted buffers -after all they are there to get the job done), but that's (engineering) life!

    Thank you again,

    Alex :-)

     

     

     

Reply

  • Hi Kari,

     What I want with my design is a single buffer near the clock input (thus the AddDriverCell line) and after that I need to have only a balanced tree all the way to the leaves (thus the LevelBalanced YES line). Just to give you a better idea of what I'm doing, I've been given a schematic of a design (and its corresponding Verilog netlist) and I was asked to transform this exact design into layout without the addition of any cell that is not already in the schematic. As I mentioned, the schematic has a single specific buffer driving the flops and assumes a balanced tree until the leaves. Sorry for the confusion.

    I know that's a weird bit of spec (usually in my designs I dont care about inserted buffers -after all they are there to get the job done), but that's (engineering) life!

    Thank you again,

    Alex :-)

     

     

     

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