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Is it not required to do ERC and antenna checks for digital implementation? In encounter we usually do metal filling. I think the purpose is to reduce antenna effect. can some body explain why we use metal filling. Is it a must for all technology nodes or is it required at 90nm and below?
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  •  ERC and antenna checks are usually part of the signoff DRC/LVS decks for the process. So yes, you do check these for digital implementation.

    Metal fill doesn't have anything to do with process antennas. Only metal connected to the gate will be part of a process antenna. Metal fill is more for manufacturing and yield. The rules for metal fill will depend on the technology and can be found in the design rule manual. Sometimes it is up to the chip designer to add the metal fill, but in other cases, the foundry prefers to add it themselves. Check with your foundry to be sure. 

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  •  ERC and antenna checks are usually part of the signoff DRC/LVS decks for the process. So yes, you do check these for digital implementation.

    Metal fill doesn't have anything to do with process antennas. Only metal connected to the gate will be part of a process antenna. Metal fill is more for manufacturing and yield. The rules for metal fill will depend on the technology and can be found in the design rule manual. Sometimes it is up to the chip designer to add the metal fill, but in other cases, the foundry prefers to add it themselves. Check with your foundry to be sure. 

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