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Verification tools

Is it not required to do ERC and antenna checks for digital implementation? In encounter we usually do metal filling. I think the purpose is to reduce antenna effect. can some body explain why we use metal filling. Is it a must for all technology nodes or is it required at 90nm and below?

Amritapuri over 16 years ago

Try this link for design rules ...

http://www.mosis.com/Technical/Designrules/guidelines.html#fill
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Kari over 16 years ago

ERC and antenna checks are usually part of the signoff DRC/LVS decks for the process. So yes, you do check these for digital implementation.
Metal fill doesn't have anything to do with process antennas. Only metal connected to the gate will be part of a process antenna. Metal fill is more for manufacturing and yield. The rules for metal fill will depend on the technology and can be found in the design rule manual. Sometimes it is up to the chip designer to add the metal fill, but in other cases, the foundry prefers to add it themselves. Check with your foundry to be sure.
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gops over 16 years ago

Thanks Kari.

So I think the DRC/LVS tool will check the ERC and Antenna as well.
I think seperate command file will be necessary for both the purpose is it?( i 'm using TSMC foundry).

Thanks N regards
gops.
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Kari over 16 years ago

It depends on the foundry and the decks, but sometimes the antenna deck is separate, and sometimes it's just part of the DRC deck. I've always seen ERC checks as part of the LVS deck, which can be annoying, since ERC checks usually need a DRC license. But I suppose it could be a separate deck as well.
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