Stats

  • Locked Locked
  • Replies 6
  • Subscribers 91
  • Views 17662
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

power routing for pads

gops
I intend to use0.18um TSMC library .When i choose the IO library i came to see that each IO cell need two VDD supply voltages one VDD(1.8V) and another VDDPST(3.3V). Also i found the VDDPAD and VSSPAD are provided for both core and IOs. I dont understand why we need VDD pad for IOs. Can anybody please tell me the reason in detail. Also please tell me reagrding power routing for IO cells.
Parents
  • gops
    Hi Kari;
    Thanks for the reply. I understood what you said.I'm sorry about my question being not clear.
    I mean to say:
     
    We use IO cells to connect the external inputs,clock ,power to the core of the chip. So we need to place the IO cells for all these pins of the chip. Usually these IO cells will be connected to the IO PADs and ESD diodes.But I have also seen pads for the IO power supply.I need to know whether I should include these cells also along with the IO cells.
     
    See the following eg:
     
    X : input;
    Y: output;
    clk:clock.
    VSS: core vdd.
    VSS:core vss.
     
    If this is the case for a design, according to my knowlede I need to put pads only for these five inputs. I need to know whather i should put pads for the IO vdd along with these IO cells.Hope the question is now clear.
Reply
  • gops
    Hi Kari;
    Thanks for the reply. I understood what you said.I'm sorry about my question being not clear.
    I mean to say:
     
    We use IO cells to connect the external inputs,clock ,power to the core of the chip. So we need to place the IO cells for all these pins of the chip. Usually these IO cells will be connected to the IO PADs and ESD diodes.But I have also seen pads for the IO power supply.I need to know whether I should include these cells also along with the IO cells.
     
    See the following eg:
     
    X : input;
    Y: output;
    clk:clock.
    VSS: core vdd.
    VSS:core vss.
     
    If this is the case for a design, according to my knowlede I need to put pads only for these five inputs. I need to know whather i should put pads for the IO vdd along with these IO cells.Hope the question is now clear.
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.