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power routing for pads

gops
I intend to use0.18um TSMC library .When i choose the IO library i came to see that each IO cell need two VDD supply voltages one VDD(1.8V) and another VDDPST(3.3V). Also i found the VDDPAD and VSSPAD are provided for both core and IOs. I dont understand why we need VDD pad for IOs. Can anybody please tell me the reason in detail. Also please tell me reagrding power routing for IO cells.

  •  I'm not sure I completely understand, and I'm not familiar with that particular library, but in general, there is a core VDD and an IO VDD. The core VDD I'm sure you're familiar with, and core-VDD IO cells feed the core grid. The power source coming into the chip connects to the pads of these IOs. The IO VDD is usually a ring that is connected by the IO cells abutting each other. These need a source from off-chip as well, which would be the pads of the io-VDD IO cells.

    Hope that makes sense,

     - Kari

  • Hi Kari;
    Thanks for the reply. I understood what you said.I'm sorry about my question being not clear.
    I mean to say:
     
    We use IO cells to connect the external inputs,clock ,power to the core of the chip. So we need to place the IO cells for all these pins of the chip. Usually these IO cells will be connected to the IO PADs and ESD diodes.But I have also seen pads for the IO power supply.I need to know whether I should include these cells also along with the IO cells.
     
    See the following eg:
     
    X : input;
    Y: output;
    clk:clock.
    VSS: core vdd.
    VSS:core vss.
     
    If this is the case for a design, according to my knowlede I need to put pads only for these five inputs. I need to know whather i should put pads for the IO vdd along with these IO cells.Hope the question is now clear.

  •  Hi Gops,

     I'm still not sure I understand - but it sounds like your IO structures consist of several pieces - is that correct? The PAD piece, the ESD piece, etc. I'm not used to these kinds of IOs. The IO cells I have worked with are all in one piece, and we just place them. There are signal IOs, clk IOs, core VDD/VSS IOs, and IO VDD/VSS IOs. These are placed around the periphery of the chip. We usually have some discretion in how many core VDD/VSS and IO VDD/VSS IOs are included, you just have to make sure there are enough to power the chip.

    I feel like I'm not helping with your question though. Sorry! :-)

    - Kari 

  • Hi Kari;
     
    What you told is right.My IO structure consists of several pieces.
     
    Any way can you please give me some details of how to route the IO ring for the following cases.
     
    a) Both core and IO at same voltage.
    b) Core and IO at different voltage.
     
    I think the VDD/VSS IO is rquired only for the second one. Can you please tell me the steps i need to follow for routing the IO ring in above two cases.
     
    Please tell me how to use a power cut cell in the design also.
     
    Thanks n regards
    gops

  •  Hi Gops,

    I don't think I've ever seen a design where core and IO power were the same voltage. However, I don't think it would matter. You would still have a core pwr/gnd ring that you add, and the IO pwr/gnd ring is connected by abutment of the IO cells. If there are gaps between IO cells, you put in IO fillers so that the rails are continuous. The corner cell is the same idea - it continues the rails around the corner.

    You would need "power cut" cells, or break cells, anywhere in the IO ring that you did not want the IO pwr/gnd to be continuous. For example, maybe most of your chip is digital but you have a small analog section, which includes analog IOs. They may be at a different voltage, or the same voltage but from a different vendor and so the pwr/gnd busses don't line up with your digital IOs. You would want to put break cells/endcap cells here to properly terminate the IO pwr/gnd rails. There can be break cells that just "cut" the busses in the middle, but could continue on either side, and there can also be endcap cells that just terminate the rails. It really depends on your design requirements where and when these are needed, as well as what is available in the IO library.

    - Kari 

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