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power routing for pads

gops
I intend to use0.18um TSMC library .When i choose the IO library i came to see that each IO cell need two VDD supply voltages one VDD(1.8V) and another VDDPST(3.3V). Also i found the VDDPAD and VSSPAD are provided for both core and IOs. I dont understand why we need VDD pad for IOs. Can anybody please tell me the reason in detail. Also please tell me reagrding power routing for IO cells.
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  •  Hi Gops,

     I'm still not sure I understand - but it sounds like your IO structures consist of several pieces - is that correct? The PAD piece, the ESD piece, etc. I'm not used to these kinds of IOs. The IO cells I have worked with are all in one piece, and we just place them. There are signal IOs, clk IOs, core VDD/VSS IOs, and IO VDD/VSS IOs. These are placed around the periphery of the chip. We usually have some discretion in how many core VDD/VSS and IO VDD/VSS IOs are included, you just have to make sure there are enough to power the chip.

    I feel like I'm not helping with your question though. Sorry! :-)

    - Kari 

Reply

  •  Hi Gops,

     I'm still not sure I understand - but it sounds like your IO structures consist of several pieces - is that correct? The PAD piece, the ESD piece, etc. I'm not used to these kinds of IOs. The IO cells I have worked with are all in one piece, and we just place them. There are signal IOs, clk IOs, core VDD/VSS IOs, and IO VDD/VSS IOs. These are placed around the periphery of the chip. We usually have some discretion in how many core VDD/VSS and IO VDD/VSS IOs are included, you just have to make sure there are enough to power the chip.

    I feel like I'm not helping with your question though. Sorry! :-)

    - Kari 

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