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Generating a LEF file from a layout

Usuomi

 Hey all-

I need to export my layout as a LEF file.  I have used CIW>File>Export...>.  When the "Virtuoso LEF Out" menu comes up I try to specify the layout cell from which to export a LEF file.  I choose "Pattern Match" at the bottom of the screen.  Then I type the name of library/cell/view (i.e. libraryTemp/adderTemp/layout). 

 I think that putting an abstract view instead of "layout" is correct.  Is this true that I need an abstract view if I want to use the LEF file in an automated layout (Magma)? 

Thanks,
Matthew

 

 

 

 

Parents

  • Hi Tongju ,

     

    I created an inverter layout(using gpdk180 technology) from schematic(no DRC error ,no LVS error ) still on running abstract generator I am getting the error

    (ABS-216): There are insufficient metal layers defined in the current design. You must define at least two metal layers in the validLayers subsection of LEFDefaultRouteSpec  constraint group of the technology file. These layers must have the layer function "metal" in the functions section.

     (ABS-218): There are no vias specified in the technology file. Ensure that the selected constraint group has a ValidVias section or at least one via is specified in the standardViaDefs subsection of the viaDefs section in the technology file.

    I repeated the layout this time maually(not from schematic ,no drc error ,no lvs error).Still getting the same errors.

    Can you suggest me what went wrong.

     

    Thanks

    gentle

     

Reply

  • Hi Tongju ,

     

    I created an inverter layout(using gpdk180 technology) from schematic(no DRC error ,no LVS error ) still on running abstract generator I am getting the error

    (ABS-216): There are insufficient metal layers defined in the current design. You must define at least two metal layers in the validLayers subsection of LEFDefaultRouteSpec  constraint group of the technology file. These layers must have the layer function "metal" in the functions section.

     (ABS-218): There are no vias specified in the technology file. Ensure that the selected constraint group has a ValidVias section or at least one via is specified in the standardViaDefs subsection of the viaDefs section in the technology file.

    I repeated the layout this time maually(not from schematic ,no drc error ,no lvs error).Still getting the same errors.

    Can you suggest me what went wrong.

     

    Thanks

    gentle

     

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