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DRC Errors and Shorts between power stripe and clock nets

Mooty

 Hi,

 

I have a lot of DRC Errors and Shorts between power stripe and clock nets.  Apparently, the routing of the clock nets simply ignores the power stripes as shown in the picture below:

[URL=http://img517.imageshack.us/my.php?image=shortingerrorsg8.png][IMG]img517.imageshack.us/.../URL]

How should I resolve this error?

Parents

  • Here's what we typically do: say you have a 6-layer design. The std cell rails are M1 (some libraries use m2, believe it or not). The next layer we have for power is m4 vertical, so you have vias from the m1 std cell rails up to the m4 stripes. Then we also do stripes on m5 and m6.

    I'm surprised that the foundry recommended m2 vertical stripes. :-) 

Reply

  • Here's what we typically do: say you have a 6-layer design. The std cell rails are M1 (some libraries use m2, believe it or not). The next layer we have for power is m4 vertical, so you have vias from the m1 std cell rails up to the m4 stripes. Then we also do stripes on m5 and m6.

    I'm surprised that the foundry recommended m2 vertical stripes. :-) 

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