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DRC Errors and Shorts between power stripe and clock nets

Mooty

 Hi,

 

I have a lot of DRC Errors and Shorts between power stripe and clock nets.  Apparently, the routing of the clock nets simply ignores the power stripes as shown in the picture below:

[URL=http://img517.imageshack.us/my.php?image=shortingerrorsg8.png][IMG]img517.imageshack.us/.../URL]

How should I resolve this error?

  •  Hi Mooty,

     Is that a metal2 pwr stripe covering an m1 pin? If you are using vertical m2 for power, you are going to have a lot of pin access issues. This picture looks to me like the router had no choice to access the m1 pin, but to short with m2. What do you think?

     - Kari

  •  Yes. I think so too. So I should be using the upper metals for it? I sticked with metal 2 because that was what the given recommended script by the foundry used.

  • Here's what we typically do: say you have a 6-layer design. The std cell rails are M1 (some libraries use m2, believe it or not). The next layer we have for power is m4 vertical, so you have vias from the m1 std cell rails up to the m4 stripes. Then we also do stripes on m5 and m6.

    I'm surprised that the foundry recommended m2 vertical stripes. :-) 

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