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Timing problems in multi cycle paths after partitioning

CT1Student

Hi everyone!

I have a path (reg2out) that initiates in a partition and then goes to the top level and, finally, to an output. So far so good, but the problem is that there is no phase shift and no cycle adjustment (this is a multi cycle path and the launch and the capture  with two different clock domains), just a big external delay and if I put it to zero I am not able to meet timing. And the required time is negative.

This problem happened to others kinds (in2reg ...)off paths also.  As far I see, this is only happing for the multi cycle paths.

 

This path in the chip top is meeting time and have no problems, just after partitioning this is happening.

 

Do you have any ideas that may explain this problem, deal with, fix it, etc?

Best Regards. 

 

Parents

  • Hi!

    Thanks for contributing!

    There is no problem in post the information that you asked, I just have to use fictitious names. ;)

     

    Lets start with the chip top constraints:

    set_output_delay -add_delay 2 -max -clock[get_clocks {clk1}] [get_ports {“MyOuput”}]

    set_multicycle_path 2 -end -hold -from[get_ports {“lots of others ports” “myOutput”}]

    set_multicycle_path 3 -setup -from[get_ports {“lots of others ports” “myOutput”}]

    set_multicycle_path 3 -setup -to[get_ports {“lots of others ports” “myOutput”}]

    set_multicycle_path 2 -end -hold -to[get_ports {“lots of others ports” “myOutput”}]

     

    Timing results for the chip top path:

     

    Path: Met Late External Delay Assertion

    Enpoint “MyOutput” clocked with leading edge of clk1.

    BeginPoint: “MyReg” triggered by leading edge of clk2.

     

    Other end arrival time: 4.167

    External Delay: 2

    Phase shift -4.166

    cycle adjustment : 16.66

    uncertainty: 0.125

    Required Time: 14.542

    Arrival Time 8.788

    Slack Time 5.754

     

    What Timing Debug window shows For the chip top level (I hope this is clear):

     

    |phase shift: -4.166| Data Delay: 8.788| External delay: 2| uncertainty: 0.125| positive slack|

    |O.E.A.T*. 4.166      | cycle adjustment: 16.166                                                                                |

      *Other End Arrival Time

     

     

    The constraints generated in timing budget just have the clocks “ clk1” and “clk2”and output delays. No multicycle path definition.

     

    Timing results for the partition:

     

    Path: Met Late External Delay Assertion

    Enpoint “MyPartitionOutput” clocked with leading edge of clk1 (same as chip top).

    BeginPoint: “MyReg” triggered by leading edge of clk2(same as chip top).

     

    Other end arrival time: 0

    External Delay: 15.238

    Phase shift 0.001

    cycle adjustment

    uncertainty: 0.125

    Required Time: -15.362

    Arrival Time 0.876

    Slack Time -16.238

     

    What Timing Debug window shows for the partition

     

    | Data Delay: 0.876| External delay: 15.238             |

    |Negative slack: -16.238                                              |

     

    The problem here is that in the partition there is no phase shift or cycle adjustment and I can´t meet timing in this way, there is no way to “capture” the data, the slack is always negative, with or without the big external delay defined in the constraints files.

     

    Thank you for your time.

    Best regards.

     
Reply

  • Hi!

    Thanks for contributing!

    There is no problem in post the information that you asked, I just have to use fictitious names. ;)

     

    Lets start with the chip top constraints:

    set_output_delay -add_delay 2 -max -clock[get_clocks {clk1}] [get_ports {“MyOuput”}]

    set_multicycle_path 2 -end -hold -from[get_ports {“lots of others ports” “myOutput”}]

    set_multicycle_path 3 -setup -from[get_ports {“lots of others ports” “myOutput”}]

    set_multicycle_path 3 -setup -to[get_ports {“lots of others ports” “myOutput”}]

    set_multicycle_path 2 -end -hold -to[get_ports {“lots of others ports” “myOutput”}]

     

    Timing results for the chip top path:

     

    Path: Met Late External Delay Assertion

    Enpoint “MyOutput” clocked with leading edge of clk1.

    BeginPoint: “MyReg” triggered by leading edge of clk2.

     

    Other end arrival time: 4.167

    External Delay: 2

    Phase shift -4.166

    cycle adjustment : 16.66

    uncertainty: 0.125

    Required Time: 14.542

    Arrival Time 8.788

    Slack Time 5.754

     

    What Timing Debug window shows For the chip top level (I hope this is clear):

     

    |phase shift: -4.166| Data Delay: 8.788| External delay: 2| uncertainty: 0.125| positive slack|

    |O.E.A.T*. 4.166      | cycle adjustment: 16.166                                                                                |

      *Other End Arrival Time

     

     

    The constraints generated in timing budget just have the clocks “ clk1” and “clk2”and output delays. No multicycle path definition.

     

    Timing results for the partition:

     

    Path: Met Late External Delay Assertion

    Enpoint “MyPartitionOutput” clocked with leading edge of clk1 (same as chip top).

    BeginPoint: “MyReg” triggered by leading edge of clk2(same as chip top).

     

    Other end arrival time: 0

    External Delay: 15.238

    Phase shift 0.001

    cycle adjustment

    uncertainty: 0.125

    Required Time: -15.362

    Arrival Time 0.876

    Slack Time -16.238

     

    What Timing Debug window shows for the partition

     

    | Data Delay: 0.876| External delay: 15.238             |

    |Negative slack: -16.238                                              |

     

    The problem here is that in the partition there is no phase shift or cycle adjustment and I can´t meet timing in this way, there is no way to “capture” the data, the slack is always negative, with or without the big external delay defined in the constraints files.

     

    Thank you for your time.

    Best regards.

     
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