Timing problems in multi cycle paths after partitioning

Can you post the multicycle constraint you have defined in your SDC file for this path and also the timing report for this path? Make sure the you have the number of cycles set to 2 (or more if needed) and make sure you have the from and to clocks defined correctly. Also check to make sure that the output pin constraint (set_output_delay) is referenced to the correct clock.

Hi!

Thanks for contributing!

There is no problem in post the information that you asked, I just have to use fictitious names. ;)

Lets start with the chip top constraints:

set_output_delay -add_delay 2 -max -clock[get_clocks {clk1}] [get_ports {“MyOuput”}]

set_multicycle_path 2 -end -hold -from[get_ports {“lots of others ports” “myOutput”}]

set_multicycle_path 3 -setup -from[get_ports {“lots of others ports” “myOutput”}]

set_multicycle_path 3 -setup -to[get_ports {“lots of others ports” “myOutput”}]

set_multicycle_path 2 -end -hold -to[get_ports {“lots of others ports” “myOutput”}]

Timing results for the chip top path:

Path: Met Late External Delay Assertion

Enpoint “MyOutput” clocked with leading edge of clk1.

BeginPoint: “MyReg” triggered by leading edge of clk2.

Other end arrival time: 4.167

External Delay: 2

Phase shift -4.166

cycle adjustment : 16.66

uncertainty: 0.125

Required Time: 14.542

Arrival Time 8.788

Slack Time 5.754

|phase shift: -4.166| Data Delay: 8.788| External delay: 2| uncertainty: 0.125| positive slack|

|O.E.A.T*. 4.166      | cycle adjustment: 16.166                                                                                |

*Other End Arrival Time

The constraints generated in timing budget just have the clocks “ clk1” and “clk2”and output delays. No multicycle path definition.

Timing results for the partition:

Path: Met Late External Delay Assertion

Enpoint “MyPartitionOutput” clocked with leading edge of clk1 (same as chip top).

BeginPoint: “MyReg” triggered by leading edge of clk2(same as chip top).

Other end arrival time: 0

External Delay: 15.238

Phase shift 0.001

cycle adjustment

uncertainty: 0.125

Required Time: -15.362

Arrival Time 0.876

Slack Time -16.238

What Timing Debug window shows for the partition

| Data Delay: 0.876| External delay: 15.238             |

|Negative slack: -16.238                                              |

The problem here is that in the partition there is no phase shift or cycle adjustment and I can´t meet timing in this way, there is no way to “capture” the data, the slack is always negative, with or without the big external delay defined in the constraints files.

Thank you for your time.

Best regards.

CT1Student said:

The constraints generated in timing budget just have the clocks “ clk1” and “clk2”and output delays. No multicycle path definition.

Ok - I misunderstood the specifics of the problem. But now I see that the issue appears to be in the generation of the timing budget constraints. I'm sorry, but this is out of my area of knowledge. In fact, I am also having issues with timing budget constraints generated for partitions. I had to submit a service request and am now working with a Cadence applications engineer on the problem.

 No problem!

Thanks for your time!!!

Have a nice week.

Best regards.

Hi

I am also facing  similar issue , did you find the solution for this problem ?

Regards

Bharath