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Timing problems in multi cycle paths after partitioning

CT1Student

Hi everyone!

I have a path (reg2out) that initiates in a partition and then goes to the top level and, finally, to an output. So far so good, but the problem is that there is no phase shift and no cycle adjustment (this is a multi cycle path and the launch and the capture  with two different clock domains), just a big external delay and if I put it to zero I am not able to meet timing. And the required time is negative.

This problem happened to others kinds (in2reg ...)off paths also.  As far I see, this is only happing for the multi cycle paths.

 

This path in the chip top is meeting time and have no problems, just after partitioning this is happening.

 

Do you have any ideas that may explain this problem, deal with, fix it, etc?

Best Regards. 

 

Parents

  • CT1Student said:

    The constraints generated in timing budget just have the clocks “ clk1” and “clk2”and output delays. No multicycle path definition.

     

    Ok - I misunderstood the specifics of the problem. But now I see that the issue appears to be in the generation of the timing budget constraints. I'm sorry, but this is out of my area of knowledge. In fact, I am also having issues with timing budget constraints generated for partitions. I had to submit a service request and am now working with a Cadence applications engineer on the problem.

Reply

  • CT1Student said:

    The constraints generated in timing budget just have the clocks “ clk1” and “clk2”and output delays. No multicycle path definition.

     

    Ok - I misunderstood the specifics of the problem. But now I see that the issue appears to be in the generation of the timing budget constraints. I'm sorry, but this is out of my area of knowledge. In fact, I am also having issues with timing budget constraints generated for partitions. I had to submit a service request and am now working with a Cadence applications engineer on the problem.

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